© 2005 Virage Logic Corporation – COMPANY CONFIDENTIAL Slide 1 EDAC Panel: Shaking Things Up in the Electronic Design Business Dr. Alex Shubat, Co-Founder, VP R&D and CTO May 2005

Slide 2 © 2005 Virage Logic Corporation – COMPANY CONFIDENTIAL SoC Design Landscape Semiconductor IP Functional IP (RTL) EDA Physical IP Infrastructure IP Wafers / Manufacturing mP DSPMPEGMP3 BUS Interface USB ….. Design Tools / Flows Foundries & IDMs Silicon Aware IP BIST, Repair, Diagnostics, Yield Enhancement, DFM Non Volatile Memory eFLASH NOVeA High Capacity Memory eDRAM 1T RAM Memory SRAM ROM CAM Logic Std Cell Libraries Metal Prog Libraries Interfaces SerDes H-S I/O Base I/O Analog PLL DLL DAC +

Slide 3 © 2005 Virage Logic Corporation – COMPANY CONFIDENTIAL Existing Solutions PHYSICAL IP Memory, Logic, I/O, Analog, Mixed-Signal INFRASTRUCTURE IP BIST, Repair, Diagnostics, Yield Enhancements BOLT ON Independently developed Physical IP and Infrastructure IP ￭ Local optimization results in sub-optimal test, diagnostics and repair ￭ Test escapes ￭ Poor yield ￭ Unpredictable quality and time-to-volume

Slide 4 © 2005 Virage Logic Corporation – COMPANY CONFIDENTIAL PHYSICAL IP Memory, Logic, I/O, Analog, Mixed-Signal INFRASTRUCTURE IP BIST, Repair, Diagnostic, Yield Enhancements INFRASTRUCTURE IP BIST, Repair, Diagnostic, Yield Enhancements Silicon Aware IP Tightly Integrated Physical And Infrastructure IP ￭ Optimal yield ￭ Higher quality ￭ Shorter time-to-volume