Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Combinational logic functions. n Static complementary logic gate structures.

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Presentation transcript:

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Combinational logic functions. n Static complementary logic gate structures.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Combinational logic expressions n Combinational logic: function value is a combination of function arguments. n A logic gate implements a particular logic function. n Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Gate design Why designing gates for logic functions is non-trivial: –may not have logic gates in the libray for all logic expressions; –a logic expression may map into gates that consume a lot of area, delay, or power.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Boolean algebra terminology n Function: f = a’b + ab’ n a is a variable; a and a’ are literals. n ab’ is a term. n A function is irredundant if no literal can be removed without changing its truth value.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Completeness n A set of functions f1, f2,... is complete iff every Boolean function can be generated by a combination of the functions. n NAND is a complete set; NOR is a complete set; {AND, OR} is not complete. n Transmission gates are not complete. n If your set of logic gates is not complete, you can’t design arbitrary logic.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Static complementary gates n Complementary: have complementary pullup (p-type) and pulldown (n-type) networks. n Static: do not rely on stored charge. n Simple, effective, reliable; hence ubiquitous.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Static complementary gate structure Pullup and pulldown networks: pullup network pulldown network V DD V SS out inputs

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Inverter a out +

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Inverter layout (tubs not shown) a out + transistors GND VDD aout tub ties

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf NAND gate + b a out

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf NAND layout + b a out b a VDD GND tub ties

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf NOR gate + b a out

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf NOR layout b a out a b VDD GND tub ties

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf AOI/OAI gates n AOI = and/or/invert; OAI = or/and/invert. n Implement larger functions. n Pullup and pulldown networks are compact: smaller area, higher speed than NAND/NOR network equivalents. n AOI312: and 3 inputs, and 1 input (dummy), and 2 inputs; or together these terms; then invert.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf AOI example out = [ab+c]’: symbolcircuit and or invert

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Pullup/pulldown network design n Pullup and pulldown networks are duals. n To design one gate, first design one network, then compute dual to get other network. n Example: design network which pulls down when output should be 0, then find dual to get pullup network.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Dual network construction dummy a bc a b c