Washington State University EE 587 SoC Design & Test Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

Core & SoC Design Examples Lecture 4 Core & SoC Design Examples

Design Flow

IP Blocks in SoCs Core Intellectual Property (IP) Virtual Component SoC jargon Core Intellectual Property (IP) Virtual Component Macro ……………

Intellectual Property (IP) Blocks

Available IP Cores

IP Market Share

VIPER – A Multiprocessor SoC Highly integrated SoC for digital TV Digital Set-Top box Viper receives, optionally decrypts, decodes, converts, and displays multiple media streams having different data formats. Besides MPEG-2 transport streams, the chip typically handles live video, audio, and various other stream types, in compressed or uncompressed formats.

VIPER Architecture

VIPER Architecture (cont’d) Two processor cores standard 32-bit MIPS RISC core (PR3940) and a 32-bit very long instruction word (VLIW) TriMedia core (TM32) The VLIW core handles Viper’s real-time multimedia processing tasks. PR3940 core is the second on-chip CPU to run the operating system and handle various control processing tasks.

General Peripherals Expansion bus interface Drawing engines Enhanced IEEE 1394 link layer Expansion bus interface Drawing engines Transport stream processor Audio interfaces Video-processing blocks

Complexity Synthesized in eight hours running on multiple CPUs 35 million transistors in 0.18 micron process Synthesized in eight hours running on multiple CPUs The design was partitioned into chiplets of 200k cells, with total nine chiplets The chip was designed to be fully scan testable

Network Processing Platform

INTEL IXP2400 Integrated Intel XScale core 8 integrated programmable microengines Integrated Intel XScale core One DRAM and two SRAM interfaces JTAG support Additional Integrated hardware

Intel’s 80-core Chip Intel’s 80-core chip In 65-nm technology with 80 single-precision, floating point cores delivers performance in excess of a teraflops while consuming less than 100 w. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores.

Overall Architecture

SoB vs. SoC

Lecture 4 SoC Test

Challenges in Testing a SoC One of the most critical challenges of this emerging discipline is manufacturing test. Core provider only delivers a description of the core design to the SOC designer. That is the IP of the vendor, who may provide only limited details of the design to the user. The user considers the core as a black-box. Accessibility to component peripherals

Conceptual Architecture of Core Test Three separate elements in the embedded core test infrastructure. Test pattern source and sink Test Access Mechanism Core test wrapper

Test Pattern Source & Sink The source generates the test stimuli and the sink compares the response to the expected response. Source and sink of a core can be implemented either off-chip, on-chip or as a combination of both The choice for a certain type of source or sink is determined by The type of circuitry in the core The type of predefined tests that come with the core Quality and cost considerations.

Test Access Mechanism (TAM) It takes care of on-chip test pattern transport. The key components of any TAM are its width and length. The width refers to the TAM’s transport capacity. The length of a TAM is the physical distance it has to bridge between the source and core or core and sink.

Implementation of TAM When implementing a TAM, we have the following options A TAM can either reuse existing functionality to transport test patterns or be formed by dedicated test access hardware. A TAM can either go through other modules on the IC or pass around those other modules. One can either have an independent access mechanism per core, or share an access mechanism with multiple cores. A test access mechanism can either be a plain signal transport medium, or may contain certain intelligent test control functions.

Core Test Wrapper Interface between the embedded core and its system chip environment. It connects the core terminals both to the rest of the IC, as well as to the TAM. It is implemented on chip.

ARM’s AMBA System An example of reusing existing functionality as TAM. In this approach, the 32-bit system bus transfers test stimuli from IC pin to the core under test and test responses vice-versa. Advantages of this approach The low additional area cost The relative simple test expansion A disadvantage of the approach is that the fixed 32-bit bus does not allow to make trade-offs between area cost and test time

Connection of System Pins to Core Terminals Connect additional wires to the core’s terminals and multiplex those onto existing IC pins testing of memories The advantage of this approach is : the embedded core can be tested as if it were a stand alone device, the translation of core-level tests into IC-level tests is simple and straightforward. The disadvantage is : it is not scalable.

Reuse of Boundary Scan

What is scan ?

Testability Measures Need approximate measure of: Difficulty of setting internal circuit lines to 0 or 1 by setting primary circuit inputs Difficulty of observing internal circuit lines by observing primary outputs Uses: Analysis of difficulty of testing internal circuit parts – redesign or add special test hardware Guidance for algorithms computing test patterns – avoid using hard-to-control lines Estimation of fault coverage Estimation of test vector length

Observability The observability of a particular circuit node is the degree to which we can observe that node at the output of an integrated circuit Measure the output of a gate within a larger circuit to check whether it operates correctly Limited number of nodes can be directly observed

Controllability The controllability of an internal circuit node within a chip is a measure of the ease of setting the node to a 1 or 0 metric Degree of difficulty of testing a particular signal within a circuit An easily controllable node would be directly settable via an input pad

Scan Design

Scan Design In test mode, all flip-flops functionally form one or more shift registers The inputs and outputs of these shift registers are made into PI/Pos Using the test mode, all flip-flops can be set to any desired states The states of the flip-flops are observed by shifting the contents of the scan register out

Scan Design Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design: Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test.

Scan Design Rules Use only clocked D-type of flip-flops for all state variables. At least one PI pin must be available for test; more pins, if available, can be used. All clocks must be controlled from PIs. Clocks must not feed data inputs of flip-flops.

Scan Flip-Flop (SFF) D Master latch Slave latch TC Q MUX Q SD CK Logic overhead MUX Q SD CK D flip-flop Master open CK Slave open t Normal mode, D selected Scan mode, SD selected TC t

Scannable Flip-flop

Bed-of-Nails Tester Concept

Need for Standard Bed-of-nails printed circuit board tester We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance Nails would hit components Reduced spacing between PCB wires Nails would short the wires PCB Tester must be replaced with built-in test delivery system -- JTAG does that Need standard System Test Port and Bus Integrate components from different vendors Test bus identical for various components One chip has test hardware for other chips

Boundary Scan Architecture