1. ~ EDA lab ~ Interconnect Verification for SOC Jing-Yang Jou Department of Electronics Engineering National Chiao Tung University Hsinchu, Taiwan E-mail: jyjou@ee.nctu.edu.twjyjou@ee.nctu.edu.tw URL: http://eda.ee.nctu.edu.tw/jyjou

2. ~ EDA lab ~ Outlines Interconnect verification –Motivation –The port order fault (POF) model –The integration verification –Automatic verification pattern generation (AVPG)

3. ~ EDA lab ~ Verification Throughput The factors that govern simulation-based verification throughput: –The speed of the simulator –The complexity of the design –The size of the test (verification) bench

4. ~ EDA lab ~ System Design Verification SOB verification –Components are designed, verified, manufactured, and tested (fault free building blocks ) –Limit to detecting faults in the interconnection among the components SOC verification –Components are design error free building blocks –Limit to detecting the misplacements of the interconnection among the components Reduce the verification complexity –Port Order Fault (POF) model

5. ~ EDA lab ~ Outlines Interconnect verification –Motivation –The port order fault (POF) model –The integration verification –Automatic verification pattern generation (AVPG)

6. ~ EDA lab ~ Basic Assumptions of the POF Model A faulty component has at least two I/O ports misplaced in the integrated design Components (IPs) are fault free Only the interconnection among the components could be faulty

7. ~ EDA lab ~ POF Variety (1/3) Type-I POF 4-bit Adder B3B3 A3A3 B2B2 A2A2 B1B1 A1A1 B0B0 A0A0 S3S3 S2S2 S1S1 S0S0 C IN C OUT

8. ~ EDA lab ~ 4-bit Adder B3B3 A3A3 B2B2 A2A2 B1B1 A1A1 B0B0 A0A0 S3S3 S2S2 S1S1 S0S0 C IN C OUT Type-II POF POF Variety (2/3)

9. ~ EDA lab ~ POF Variety (3/3) 4-bit Adder B3B3 A3A3 B2B2 A2A2 B1B1 A1A1 B0B0 A0A0 S3S3 S2S2 S1S1 S0S0 C IN C OUT Type-III POF

10. ~ EDA lab ~ Typical Errors in the Integrated SOC Design VCs are connected with wrong port orders VCs with incompatible communication protocols are directly connected –PCI vs. AMBA Interface parameters are not properly configured –Baud rate 2400 vs. baud rate 9600 TX RX TX RX TX RX TX RX

11. ~ EDA lab ~ Outlines Interconnect verification –Motivation –The port order fault (POF) model –The integration verification –Automatic verification pattern generation (AVPG)

12. ~ EDA lab ~ Interconnect Testing IP 2 IP 1 wrapper Apply patterns Observe responses

13. ~ EDA lab ~ Interconnect Verification IP 2 IP 1 wrapper Apply patterns Observe responses

14. ~ EDA lab ~ Integration Verification

15. ~ EDA lab ~ Verifying the interconnect A, B, and C –Apply patterns T to PIs and observe responses R from POs The generation of T depends on the functionalities of BLK1 ~BLK6 Complexity of cores increases and more cores are involved –T becomes harder to generate Solution ? Integration Verification

16. ~ EDA lab ~ System Chip with P1500 Cores

17. ~ EDA lab ~ IEEE P1500 –Establishes the mechanism that test patterns of any CUT can be applied to PIs of the system chip and test results can be propagated to POs of the system chip via user defined TAMs –Pre-defined operations: core-internal test, core- external test, bypass, isolation, and normal modes Integration Verification

18. ~ EDA lab ~ Interconnect Verification IP 2 IP 1 wrapper Apply patterns Observe responses

19. ~ EDA lab ~ Integration Verification

20. ~ EDA lab ~ Integration Verification

21. ~ EDA lab ~ Verification Features Reduce the complexity of POF verification –Focus on the functionality of the added block solely when generating the verification patterns Exercise the core via the normal operation path to verify the interconnect –Consistency check of simulation results and expected ones Reuse the hardware overhead incurred in the testing phase

22. ~ EDA lab ~ Outlines Interconnect verification –Motivation –The port order fault (POF) model –The integration verification –Automatic verification pattern generation (AVPG)

23. ~ EDA lab ~ Automatic Verification Pattern Generation (AVPG) Fault Activation –All N!-1 POFs have to be activated Fault Propagation –Determined by simulation outputs Undetected Port Sequences (UPSs) Calculation –Outputs analysis

24. ~ EDA lab ~ Experimental Results

25. ~ EDA lab ~ Interconnect verification provides a sufficient high level of confidence on verifying the correctness of the core-based system (SOC) design Proposed AVPG can generate efficient verification patterns with high POF coverage Conclusions