EE 261 – Introduction to Logic Circuits Module #3 - Digital Circuits Topics Digital Signaling Logic Gates Gates at the Transistor Level CMOS Static Behavior CMOS Dynamic Behavior Textbook Reading Assignments 3.1–3.6 Practice Problems 3.1, 3.5, 3.7, 3.13, 3.27(a,c,e,g) Graded Components of this Module 2 homeworks, 2 discussions, 1 quiz (all online)

EE 261 – Introduction to Logic Circuits Module #3 - Digital Circuits What you should be able to do after this module Draw the Symbols, Equation, and Truth Table for Basic Logic Gates Draw the transistor-level circuit of a CMOS Inverter, NAND-Gate, and NOR-Gate Describe CMOS Logic Static Behaviors (Noise Margins, Load Current, Fan-In/Out) Describe CMOS Logic Dynamic Behaviors (Delay, Power, SSN, ESD)

Digital Signaling Digital Signaling - A binary number system contains two symbols and a set of operations - But what does a '0' or a '1' look like in real life? - Many things can represents 0's and 1's, but we are interested in representing them using "electrical signals" Logic Signals - to represent a 0 or 1, we use an electrical signal (voltage or current) - let's focus on voltage to begin with

Digital Signaling Logic Signals - a logic signal may look like this… - we define a threshold to represent when we consider the signal a: LOGIC 0 or LOGIC 1 v(t) vthreshold t

Digital Signaling Logic Signals - we say that the signal is: LOW = when the voltage is < Vthreshold HIGH = when the voltage is > Vthreshold Positive Logic : when a LOW represents a 0 when a HIGH represents a 1 Negative Logic : when a LOW represents a 1 when a HIGH represents a 0 v(t) vthreshold t

1 1 1 1 Digital Signaling Using Positive Logic v(t) Noise - Digital signals have an advantage when noise is present v(t) 1 1 vthreshold t v(t) 1 1 vthreshold t

Logic Gates Logic Circuit - a circuit that produces logic outputs depending on the logic inputs ex) Combinational Logic - The outputs of the logic circuit depend ONLY on the current input values Logic

Logic Gates Truth Table - a table that lists the output values for a given set of inputs in a logic circuit - for "n" inputs, there are 2n possible input combinations ex) n = 2 In1 In2 Output 0 0 0 0 1 0 1 0 1 1 1 0 - when designing a logic circuit, we typically start with the truth table

Logic Gates Logic Gates - the basic building blocks of digital logic - these represent the most simple logic operations BUFFER Gate - Out = In 1

Logic Gates NOT Gate - also called an inverter - Out = In' AND Gate - Out = A•B = AB

Logic Gates OR Gate - Out = A + B

Logic Gates XOR Gate - Out = A  B NAND Gate - Out = (A•B)'

Logic Gates NOR Gate - Out = (A + B)' XNOR Gate - Out = (A  B )'

Logic Gates Timing Diagram - Real systems operate with respect to time - When we draw out the logic waveforms vs. time it is called a "Timing Diagram" A B Z t

Logic Gates Simple Logic Circuits - we use the basic gates to construct more complex combinational circuits - using our notation (•, +, , ') we can write the "logic expression" for complex circuits Z = (A  B) + C

Logic Gates Delay - There is delay through each gate. In order to have a valid output, we must wait for the signals to propagate through all the gates in the circuit - this delay can be described using timing diagrams Conversion to Truth Tables - From a circuit diagram, we can draw the timing diagram & truth table - From the truth table, we can draw the timing diagram & circuit diagram - From the timing diagram, we can draw the circuit diagram & truth table

Gates at the Transistor Level Logic Gates - we've seen the basic logic gates that we use to form more complex logic expressions BUF, INV, AND, NAND, OR, NOR, XOR, XNOR Logic Signaling - we've seen how we use an electrical signal to represent and transmit logic values A 1 1 1 B 1 1 1 1 t

Gates at the Transistor Level Logic Families - now we want to see how we actually create these circuits and signals using electronics - there are different ways (or circuits) to implement logic gates - the circuits are designed to interface with other circuits with the same type of design - a collection of IC's designed to interface with each other is called a "Logic Family" - the most common families we deal with in school are: 1) CMOS 2) TTL

Gates at the Transistor Level MOSFET - stands for Metal Oxide Semiconductor Field Effect Transistor - there are two types of MOSFET's 1) NMOS 2) PMOS - this is analogous to bipolar transistors (npn, pnp) - a MOSFET is a 3 terminal device - this device can be thought of as a "voltage controlled resistor" - a change on the gate voltage changes the resistance between the Drain and Source - we can turn ON/OFF the flow of current by altering the voltage on the Gate Drain Gate Source

Gates at the Transistor Level NMOS - an NMOS will allow current to flow between the Drain and Source when: VGS > 0 - When VGS = 0, no current flows - Cross Section of NMOS Construction D S G + VGS - IDS Gate Source Metal Drain Oxide p n n Semiconductor

Gates at the Transistor Level PMOS - a PMOS will allow current to flow between the Drain and Source when: VGS < 0 - When VGS = 0, no current flows - Cross Section of PMOS Construction - VGS + S IDS G D Gate Source Metal Drain Oxide n p p Semiconductor

Gates at the Transistor Level Basic NMOS Operation - we typically call the power supply VDD (+5v, +3.3v, +2.5v, +1.8v) - We typically call the ground either GND or VSS (0v) D S G OFF VDD GND Logic 0 ON Logic 1

Gates at the Transistor Level Basic PMOS Operation VDD VDD S S Logic 0 G ON Logic 1 G OFF S D GND GND

Gates at the Transistor Level CMOS - we now have two complementary switches S G ON VDD GND Logic 0 D OFF Logic 1 PMOS D S G OFF VDD GND Logic 0 D S G ON VDD GND Logic 1 NMOS

Gates at the Transistor Level CMOS - CMOS = Complementary MOS - The complementary structure gives a way to always connect the output to either VDD or GND - Consider the following circuit VDD S G PMOS D Input Output D NMOS G S GND

Gates at the Transistor Level CMOS - When the Input = 0, the Output is connected to VDD VDD S G PMOS=ON D Input = 0 Output=1 D NMOS=OFF G S GND

Gates at the Transistor Level CMOS - When the Input = 1, the Output is connected to GND - this is how we construct a CMOS Inverter VDD S G PMOS=OFF D Input = 1 Output=0 D NMOS=ON G S GND

Gates at the Transistor Level CMOS Inverter - Graphically, this looks like: VDD = HIGH Vin GND = LOW Vout t

Gates at the Transistor Level MOSFET Level - we have two complementary switches VDD S Input = 0, PMOS = ON Input = 1, PMOS = OFF G S GND VDD D Input = 0, NMOS = OFF Input = 1, NMOS = ON G S GND

Gates at the Transistor Level MOSFET Level - another way to draw these is as follows: VDD S Input = 0, PMOS = ON Input = 1, PMOS = OFF G S GND VDD D Input = 0, NMOS = OFF Input = 1, NMOS = ON G S GND

Gates at the Transistor Level CMOS Gates - NMOS and PMOS transistors can be used together to form logic gates - the complementary structure is desired because the output is always being driven with a MOSFET - HIGH = a PMOS is ON and connecting the output to the VDD supply all of the NMOS's are OFF - LOW = an NMOS is ON and connecting the output to the VSS supply (GND) all of the PMOS's are OFF

Gates at the Transistor Level CMOS Inverter Input = 0 Input = 1 VDD VDD PMOS = ON S PMOS = OFF S G G S 1 S ILOAD ILOAD 1 D D G G S NMOS = OFF S NMOS = ON GND GND

Gates at the Transistor Level CMOS NAND Gate - PMOS's in parallel provide an OR'ing structure for the connection to VDD - NMOS's in series provide an AND'ing structure for the connection to GND VDD VDD A B Output A B GND

Gates at the Transistor Level CMOS NAND Gate - We can increase the number of inputs to the NAND gate by - adding more PMOS's in parallel - adding more NMOS's in series VDD VDD A B Output A B

Gates at the Transistor Level FAN-IN - Can we increase the number of inputs infinitely? - No, because…. - adding PMOS's in parallel decreases the ON resistance and will consume too much power - the capacitance from all of the gates on a single input line will slow down the circuit - We define "Fan-In" as the number of inputs that a given device can have ex) CMOS NAND : Fan-In = 6 - the datasheet for the device will specify this

Gates at the Transistor Level CMOS NOR Gate - PMOS's in series provide an AND'ing structure for the connection to VDD - NMOS's in parallel provide an OR'ing structure for the connection to GND VDD A B Output B A GND GND

Gates at the Transistor Level CMOS NOR Gate - We can increase the number of inputs to the NOR gate by - adding more PMOS's in series - adding more NMOS's in parallel - Again, Fan-In applies A B Output B A GND GND

Gates at the Transistor Level Non-Inverting Gates - What about AND, OR, and BUF? - In CMOS, we use INV, NOR, NAND for everything - BUF Gate = 2 Inverters - AND Gate = NAND and Inverter - OR Gate = NOR and Inverter

CMOS Static Behavior Vin Vout Logic Levels - We need to define boundaries when the signal is considered HIGH or LOW - what is the logic level in the middle region? VDD = HIGH Vin HIGH LOW GND = LOW Vout t

CMOS Static Behavior Vout Vin CMOS Static Behavior - "Static" or "DC" refers to the gate's operation when the inputs are NOT changing - also called "Steady State" - if we plotted Vout vs. Vin of an Inverter, we would get… Vout Logic HIGH Logic LOW Vin

CMOS Static Behavior Vout Vin CMOS Static Behavior - the region in the middle is not definitely a HIGH or a LOW because of: - Power Supply Variation - Process - Noise Vout ??? Vin

CMOS Static Behavior Specification - we need to be able to guarantee operation of the gate over all possible conditions - the limits on guaranteed operation are called "specifications" - Specifications can give limits on the worst case situations - Specifications can also give limits on typical situations

CMOS Static Behavior Vin Input Specifications VIHmin : Minimum input voltage guaranteed to be recognized as a HIGH VILmax : Maximum input voltage guaranteed to be recognized as a LOW VDD HIGH VIHmin Vin VILmax LOW VSS

CMOS Static Behavior Vout Output Specifications VOHmin : Minimum output voltage guaranteed when driving a HIGH VOLmax : Maximum output voltage guaranteed when driving a LOW VDD HIGH VOHmin Vout VOLmax LOW VSS

CMOS Static Behavior Vout Vin Noise Margin HIGH State Noise Margin : (VOHmin - VIHmin) LOW State Noise Margin : (VILmax - VOLmax) Vout Vin VDD VDD HIGH HIGH VOHmin Noise Margin VIHmin VILmax Noise Margin LOW VOLmax LOW VSS VSS

CMOS Static Behavior Leakage Current - Ideally, a CMOS device driving another CMOS device will have ZERO output current - However, in reality there is a small amount of current that flows due to the implementation of the MOS's in real materials - there is a specification that tells us how much current can be expected to flow IIH : Maximum current flowing when driving a HIGH IIL : Maximum current flowing when driving a LOW

CMOS Static Behavior Resistive Loads - Sometimes we don't drive just CMOS loads - we may have resistors that are attached to the receiver - When resistors are attached, we must account for the voltage drop across the resistors when checking VILmax , VIHmin

CMOS Static Behavior Driver Models - We can model the MOSFET's as resistors - They have different resistance when they are ON (low) versus when they are OFF (high) - We can typically ignore the OFF resistance when considering the equivalent driver model - We use the driver resistance along with the load resistors to find the Input Voltages (via KVL, KCL, Ohm's Law)

CMOS Static Behavior Rp CMOS DRIVING HIGH CMOS Driving a HIGH Equivalent Driver Model VDD VDD PMOS = ON S G Rp S ILOAD ILOAD 1 D G S NMOS = OFF GND

CMOS Static Behavior Rn CMOS DRIVING LOW CMOS Driving a LOW Equivalent Driver Model VDD PMOS = OFF S G 1 S ILOAD ILOAD D Rn G S NMOS = ON VSS GND

CMOS Static Behavior Rp RL CMOS Resistive Loads - we need to find the voltage drop across the resistors to ensure we're meeting the input spec VDD Rp VIN > VIHmin RL

CMOS Static Behavior Load Current - there is a spec on how much current can be driven by the CMOS device - in addition to verifying that we're meeting the input voltage spec of the receiver, we must also check to see that we're not exceeding the load current spec of the driver IOH : Maximum current that can be sourced when driving a HIGH IOL : Maximum current that can be sourced when driving a LOW

CMOS Static Behavior CMOS Static Behavior - Summary of static characteristics: - Logic Levels - Noise Margin - Static DC Current - Resistive Loads - Output Current - Summary of static specifications: VIHmin : Minimum input voltage guaranteed to be recognized as a HIGH VILmax : Maximum input voltage guaranteed to be recognized as a LOW VOHmin : Minimum output voltage guaranteed when driving a HIGH VOLmax : Maximum output voltage guaranteed when driving a LOW IIH : Maximum current flowing when driving a HIGH IIL : Maximum current flowing when driving a LOW IOH : Maximum current that can be sourced when driving a HIGH IOL : Maximum current that can be sourced when driving a LOW

CMOS Static Behavior FAN-OUT - the Maximum # of devices that a gate can drive - depends on IOH and IOL - It may differ for driving HIGH vs. driving LOW (we always take the minimum #) - NOTE: We are only considering DC Fan Out

CMOS Static Behavior Datasheets - a datasheet is a document that a device manufacture provides - this lists all of the specifications for the part - the conditions for each specification are listed - we use datasheets to understand the operation of a part and whether it will work in our design

CMOS Static Behavior ESD - Electrostatic Discharge - moving objects accumulate charge - CMOS devices are very sensitive to ESD - if a large amount of ESD is discharged onto a device, it can destroy the device - the ESD has the energy to - re-diffuse doped regions - blow metal traces - fuse materials together to form a new compound - to avoid, we can: - use ESD protection circuitry within the device - discharge ourselves before touching the device

CMOS Static Behavior Latch-Up - there are parasitic bipolar transistors within the MOSFET structure (npn, pnp) - if given enough energy, these bipolar transistors can get into a positive feedback configuration and begin to conduct current through the silicon - this is a problem because a large amount of current will flow and cannot be turned off - latch up will typically burn out the IC

CMOS Static Behavior Latch-Up Prevention - at manufacturing, the npn / pnp paths are isolated from each other using guard rings

CMOS Dynamic Behavior CMOS Dynamic Behavior - We've looked at the following static characteristics: - Logic Levels - Noise Margin - Static DC Current - Resistive Loads - Output Current - Dynamic Behavior refers to when the Inputs/Outputs are switching - Also called "AC" performance - Dynamic behavior describes: 1) Speed 2) Power

CMOS Dynamic Behavior Speed - The speed of a gate depends on (i) Transition Time (ii) Propagation Delay Transition Time - the time it takes for the Output to change between logic levels

CMOS Dynamic Behavior Vout t Speed : Transition Time - we can define the "rise time and "fall time" as the time it takes to pass through the uncertainty region Vout HIGH LOW t trise tfall

CMOS Dynamic Behavior Rp RL CP Cint CL Speed : Transition Time - transition time depends on 1) The ON Resistance of the driver 2) The capacitance of the load - for AC analysis, the DC resistance and Voltage of the load have no effect - the capacitance comes from a) Output driver b) Wiring/Interconnect c) Input circuit VDD Rp RL CP Cint CL

CMOS Dynamic Behavior R C Speed : Transition Time - we can model the AC circuit as one RC - the Time Constant is RC  = RC VIN R VOUT C

CMOS Dynamic Behavior R C Speed : Transition Time Rising Edge "Exponential Approach" VOUT = VIN·(1 – e(-t/RC) ) - we assume the capacitor is NOT charged Falling Edge "Exponential Decay" VOUT = VIN·e(-t/RC) - we assume the capacitor is fully charged - We set VIN to its steady state value at t=0 (i.e., VIN=VDD) VIN R VOUT C

CMOS Dynamic Behavior Vin Vout t Speed : Propagation Delay - the time it takes for a change on the Input to result in a change on the output - we use an inverter model for this delay where: tpLH = Δt from input falling edge to output rising edge tpHL = Δt from input rising edge to output falling edge - we use the midpoints of the transitions Vin Vout t tpLH tpHL

CMOS Dynamic Behavior Power Consumption - there are two components of power consumption 1) DC Power : when inputs are static (quiescent) - typically low in CMOS - this is also called "leakage" 2) AC Power : when outputs are switching - largest contributor to overall power (i) Short Circuit Power (ii) Load Power

CMOS Dynamic Behavior Power Consumption - Short Circuit Power - at the moment of time when an output is half way through its transition, both the PMOS and NMOS are on. - this creates a path from VDD to GND PSC = PT = CPD · VDD · f - CPD is the "Power Dissipation Capacitance" (given by MFN) VDD PMOS = ON S G VDD/2 S D ISC G S NMOS = ON GND

CMOS Dynamic Behavior CL Power Consumption - Load Power - the power is takes to charge & discharge the load capacitance PL = CL · VDD2 · f - CL is the sum of all load capacitance (driver + interconnect + receiver) VDD PMOS = ON S G S D CL IL G NMOS = OFF S GND

CMOS Dynamic Behavior CL Power Consumption - Total Power PD = (CPD + CL) · VDD2 · f - CL tends to dominate VDD PMOS = ON S G S D CL IL ISC G NMOS = OFF S GND

CMOS Dynamic Behavior CL Simultaneous Switching Noise (SSN) - What happens when we switch logic levels with a capacitive load? - the capacitor looks like a short at AC (or when transitioning) VDD PMOS = ON S G S D CL IL G NMOS = OFF S GND

CMOS Dynamic Behavior Simultaneous Switching Noise (SSN) - this causes a large instantaneous current to be drawn from the power supply - the power supply cannot supply this sudden change in current because it has a much slower response - we can think of the power supply as a large capacitor that stores our charge. The interconnect that supplies this charge to our device tends to be inductive and resistive. - when we draw current quickly through the interconnect, there is voltage drop - as a result, the power supply voltage will begin to "droop" as seen by our device

CMOS Dynamic Behavior R,L CDecoupling CL Simultaneous Switching Noise (SSN) - "Decoupling Capacitors" - we can put decoupling (or bypass) capacitors near our device to provide the faster, instantaneous current draw due to switching logic levels. R,L VDD CDecoupling PMOS = ON S G S D CL IL G NMOS = OFF S GND

CMOS Dynamic Behavior + L VL - CL Simultaneous Switching Noise (SSN) - "Ground Bounce" - when the interconnect on the IC is inductive, we will get a voltage drop when instantaneous current is drawn. VL = L (di/dt) - this causes the VDD (or GND) on-chip to be different from the VDD (or GND) in the system. - this is called "Ground Bounce" - this leads to inadvertent switching of logic circuits - this problem becomes more sever when multiple signals share the same VDD or GND pin VDD L + VL - PMOS = ON S G S D CL IL G NMOS = OFF S GND

Module Overview Topics - Truth Tables - Logic Gates - Simple Logic Circuits - Timing Diagrams - MOSFETS - NMOS, PMOS, CMOS - CMOS Inverter - CMOS NAND - CMOS NOR - CMOS AND,OR,BUF - CMOS Static Behavior - Input Specs - Output Specs - Noise Margin - Leakage - Resistive Loads - Fan-In / Fan-Out - Latch-Up - CMOS Dynamic Behavior - transition time / propagation delay - power consumption (SC & Load) - Decoupling - Ground Bounce / SSN