PolyFuse OTP Cell A CMOS compatible PolyFuse element used in an One Time Programmable circuit Johannes Fellner austriamicrosystems AG 08.04.2005.

Slides:



Advertisements
Similar presentations
ECE 353 Introduction to Microprocessor Systems
Advertisements

Introduction to MOSFETs
DYNAMIC ELECTRICITY.
Tunable Sensors for Process-Aware Voltage Scaling
Transistors (MOSFETs)
Physical structure of a n-channel device:
Wires.
Unijunction Transistor
BEOL Al & Cu.
Metal Oxide Semiconductor Field Effect Transistors
Introduction Since the beginning of the oil crises, which remarkably influenced power development programs all over the world, massive technological and.
Twin Logic Gates – Improved Logic Reliability by Redundancy concerning Gate Oxide Breakdown Hagen Sämrow, Claas Cornelius, Frank Sill, Andreas Tockhorn,
Principles & Applications
Metal Semiconductor Field Effect Transistors
Overview Memory definitions Random Access Memory (RAM)
Outline Introduction – “Is there a limit?”
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 22: Material Review Prof. Sherief Reda Division of Engineering, Brown University.
Memory and Advanced Digital Circuits 1.
Circuit characterization and Performance Estimation
McGraw-Hill © 2008 The McGraw-Hill Companies Inc. All rights reserved. Electronics Principles & Applications Seventh Edition Chapter 3 Diodes (student.
Instructor:Po-Yu Kuo 教師:郭柏佑
Worcester Polytechnic Institute
Chapter 7 DC Biasing Circuits
ELECTRICITY Chapter 13.2 – 13.3 VOLTAGE / AMPERAGE / WIRE / BATTERY / SERIES / PARALLEL / MULTIMETER.
FET ( Field Effect Transistor)
Qualitative Discussion of MOS Transistors. Big Picture ES220 (Electric Circuits) – R, L, C, transformer, op-amp ES230 (Electronics I) – Diodes – BJT –
Analog Layout.
Principles & Applications
1 CMOS Temperature Sensor with Ring Oscillator for Mobile DRAM Self-refresh Control IEEE International Symposium on Circuits and Systems, Chan-Kyung.
© 2013 The McGraw-Hill Companies, Inc. All rights reserved. McGraw-Hill 3-1 Electronics Principles & Applications Eighth Edition Chapter 3 Diodes Charles.
EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 4 Programmable.
1 Monolithic Pixel Sensor in SOI Technology - First Test Results H. Niemiec, M. Koziel, T. Klatka, W. Kucewicz, S. Kuta, W. Machowski, M. Sapor University.
CMOS Analog Design Using All-Region MOSFET Modeling 1 CMOS Analog Design Using All-region MOSFET Modeling Chapter 3 CMOS technology, components, and layout.
Qualitative Discussion of MOS Transistors. Big Picture ES230 – Diodes – BJT – Op-Amps ES330 – Applications of Op-Amps – CMOS Analog applications Digital.
Low Power – High Speed MCML Circuits (II)
Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.
Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Pseudo-nMOS gates. n DCVS logic. n Domino gates. n Design-for-yield. n Gates as IP.
Washington State University
Chapter 19 Review Current and Resistance. 1. A current of 2 amps flows for 30 seconds. How much charge is transferred?
EE141 © Digital Integrated Circuits 2nd Devices 1 Goal of this lecture  Present understanding of device operation  nMOS/pMOS as switches  How to design.
VLSI Design Lecture 3: Parasitics of CMOS Wires Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Harris’s lecture.
Introduction to MOS Transistors Section Outline Similarity Between BJT & MOS Introductory Device Physics Small Signal Model.
11. 9/15 2 Figure A 2 M+N -bit memory chip organized as an array of 2 M rows  2 N columns. Memory SRAM organization organized as an array of 2.
1 Overview of Fabrication Processes of MOSFETs and Layout Design Rules.
EE210 Digital Electronics Class Lecture 6 May 08, 2008.
CMOS VLSI Fabrication.
CHAPTER 6: MOSFET & RELATED DEVICES CHAPTER 6: MOSFET & RELATED DEVICES Part 2.
Chapter 4 DC Biasing–BJTs. Copyright ©2009 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Electronic Devices and.
FPGA Based System Design Dr. Nazar Abbas Saqib NUST Institute of Information Technology (NIIT) Lecture 2: Programming Technolgies
CP 208 Digital Electronics Class Lecture 6 March 4, 2009.
Transistors (MOSFETs)
EMT 112 / 4 ANALOGUE ELECTRONICS Self-Reading Power Transistor – BJT & MOSFET.
Written by Whitney J. Wadlow
EENG 3520: Electronics II Lecture 3 Oluwayomi Adamo.
DESIGN OF A 9MHZ 15KW CW AMPLIFIER FOR RHIC Shane Dillon CTO.
POLY FUSE a n EW STANDARD OF CIRCUIT PROTECTION
Basic Electronics for Computer Engineering 1 Chapter 3 Ohm’s Law.
STT-RAM Feasibility Study Amr Amin UCLA Jan 2010.
Circuit characterization and Performance Estimation
BURGLAR ALARM ON WINDOW GLASS BREAKING
Digital Electronics Class Lecture October 22, 2008
FM TRANSMITTER 2 KM RANGE FOR YAGI ANTENNA
Metal Semiconductor Field Effect Transistors
20-NM CMOS DESIGN.
منبع: & کتابMICROELECTRONIC CIRCUITS 5/e Sedra/Smith
Transistors (MOSFETs)
Qualitative Discussion of MOS Transistors
Topic 3 Continued: Resistors
9 Transistor Fundamentals.
Linear Technology Corporation
Presentation transcript:

PolyFuse OTP Cell A CMOS compatible PolyFuse element used in an One Time Programmable circuit Johannes Fellner austriamicrosystems AG 08.04.2005

Purpose Design an OTP Element in a Standard 0.35um CMOS Process PolyFuse element defined Programming within process specification High lifetime & reliability Implementation of the OTP Element into an IP-Block Infield programming option High programming yield

Outlook Introduction into PolyFuse OTP Programming Characteristics Cross Sections Reliability and Yield WAT Implementation Design Issues for IP Block Summary

Introduction PolyFuse used as an OTP base element Poly Silicon with Tungsten Silizide Low ohmic standard resistance (<100W) High ohmic after programming (>10kW)

PolyFuse Element Programming Features Programming in standard CMOS process Current programming Infield programming possible

Programming Characteristic Iprog mA Vprog V tprog 0µs 1µs 2µs 3µs Ilinear: Linear resistor characteristics Iheat: Temp. is raising Imelt: Tungsten Silicide is melting Imax: Maximum current of minimum resistance Imin: Local current min. Iosc: Oscillation because of break Imax Imelt Imin Ialloy Iheat Ilinear Iosc Ialloy: No autonomous current pinch off

Typical Current Programmed Poly Fuse Cross Section Typical Current Programmed Poly Fuse Active PolyFuse region no longer has Tungsten included High ohmic stable alloy Local break of a few nm Minimal lifetime drift of the resistance value Substrate Field Oxide Poly Silicon Tungsten Silicide Tungsten Plug approx. 40nm

Low Current Programmed Poly Fuse Cross Section Low Current Programmed Poly Fuse Inhomogenious temperature gradient during programming Low ohmic resistor Lifetime drift to higher resistor values Tungsten Plug Field Oxide Tungsten Plug Tungsten Silicide Tungsten Silicide Poly Silicon Poly Silicon Field Oxide Substrate Substrate

Low Current Programmed Poly Fuse Cross Section Low Current Programmed Poly Fuse High energy is forcing the Tungsten seperation Break before Tungsten completely removed Relatively high ohmic resistor Lifetime drift to lower resistor values possible Tungsten Plug Field Oxide Tungsten Plug Tungsten HALO Tungsten Silicide Tungsten Silicide Poly Silicon Poly Silicon Tungsten Field Oxide Substrate Substrate

Reliability Investigations Lifetime Drift over Time 2000h BurnIn@125 °C HTOL Test JESD22-108 Lifetime Drift Investigated for typical current programmed PolyFuses low current programmed PolyFuses high current programmed PolyFuses

Yield Analysis Testchip with Geometrical Variations Variation of size of programming transistor Variation of PolyFuse length and width Design Of Experiment (DOE) Run With of Stack: Tungsten Silicide - Poly Silicon Tungsten Silicide thickness variation Poly Silicon thickness variation Analysis Programming within specified limits Variable temperature and supply specifications

Process Control WAT Structure Measurements PolyFuse Element Burning NMOS Transistor Measurements Resistor of unprogrammed PolyFuse Resistor of programmed PolyFuse Current of Burning Transistor

Design Issues IP Blocks with PolyFuses Designed 32 bit 128bit Optimized Programming Path PolyFuse Related programming transistor Special Test Function to guarantee lifetime stability for infield programming

Design Requirement Requirements For Lifetime Stability A programmed PolyFuse resistance must be larger than 10kW after programming The resistance of a programmed PolyFuse is checked at 1kW during lifetime operation This margin ensures proper operation of programmed PolyFuses over lifetime Requirement for Infield Programming Testmode to measure the unprogrammed PolyFuse resistance (<100W)

Base Cell Principle Schematic PolyFuse Element Programming Transistor Current Mirror Testmodes

Base Cell Principle Layout PROM Storage RAM Access LOADing Mode PROGramming Mode Optional Parallel Out

OTP Block Principle Layout of OTP Block 32bit and 128bit Version 32bit Parallel Out Address Decoder Autoloader at Startup Combination up to 2kbit

Conclusion Reliable Programming Conditions Programmable over whole Process Range Lifetime Stability High Programming Yield Process Control Infield Programming Option