Design Considerations in CLBs for Deep Sub-Micron Technologies Louis Alarcón Octavian Florescu.

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Presentation transcript:

Design Considerations in CLBs for Deep Sub-Micron Technologies Louis Alarcón Octavian Florescu

Motivation As technology scales… –The effects due to process variations will become more pronounced. Regular structures are needed to mitigate these effects. –Leakage will increase as the V TH are scaled. Low leakage architectures will be needed to control stand-by power.

Configurable Logic Block Stack –Regular –Low Leakage –Slow due to RC delay Current Sensing –Recover performance loss through smaller voltage swings. Data Inputs S S OUT CLK Program Bits Pass Transistor Stack Pass Transistor Stack Current Sense Current Sense

Root Input A B S S P0P0 Programming (P 0, P 1, P 2, P 3 ) Logic to sense amp A B B B The Stack Inverted multiplexer tree “pseudo-differential” currents at the outputs Data inputs: 4 Program bits: 16

I ON I OFF  0 V1V1 V2V2 I BIAS I1I1  V = V 1 - V 2 > 0 V1V1 V2V2 I ON I OFF CLB V1V1 V2V2 I ON I OFF DCVSL-based Sense Amplifier (DCVSL-SA) Clamped Bit-Line Sense Amplifier (CBL) Conditional Precharge Sense Amplifier (CP) Sense Amplifier Topologies

I ON I OFF  0 V1V1 V2V2 I BIAS I1I1  V = V 1 - V 2 > 0 V1V1 V2V2 I ON I OFF CLB V1V1 V2V2 I ON I OFF DCVSL-based Sense Amplifier (DCVSL-SA) Clamped Bit-Line Sense Amplifier (CBL) Conditional Precharge Sense Amplifier (CP) Sense Amplifier Topologies

I ON I OFF  0 V1V1 V2V2 I BIAS I1I1  V = V 1 - V 2 > 0 V1V1 V2V2 I ON I OFF CLB V1V1 V2V2 I ON I OFF DCVSL-based Sense Amplifier (DCVSL-SA) Clamped Bit-Line Sense Amplifier (CBL) Conditional Precharge Sense Amplifier (CP) Sense Amplifier Topologies

I ON I OFF  0 V1V1 V2V2 I BIAS I1I1  V = V 1 - V 2 > 0 V1V1 V2V2 I ON I OFF CLB V1V1 V2V2 I ON I OFF DCVSL-based Sense Amplifier (DCVSL-SA) Clamped Bit-Line Sense Amplifier (CBL) Conditional Precharge Sense Amplifier (CP) Sense Amplifier Topologies

EDP and Leakage CMOS TG CBL CP DCVSL-SA Looks too good to be true? It probably is… EDP CMOS TG CBL CP DCVSL-SA Leakage Current

CLB (Stack) CLB (Stack) CP SA CP SA I ON I OFF  V SA Root Input I ON  V SA Process Variation and Mismatch  V should be > 0 for proper sensing I ON,min needed by the sense amplifier upsize

Sizing for Yield CBL CP DCVSL-SA CBL CP DCVSL-SA EDP Leakage Current Yield Target: 99% (Monte Carlo process and mismatch simulations) needs to be verified in silicon

Constant Yield Lines Solid line has a 99% yield over all process corners. –Overkill? The yield increases as V DD increases CP (Upsized) CLB: 10x CP Sense Amp: 2x CP EDP CP Performance Loss

Constant Yield Lines Dash-dotted line represents a constant Yield Line. Size of CLB tailored to desired Yield and V DD. 99% yield line A B CP (Upsized) CLB: 10x CP Sense Amp: 2x CP Yield B = Yield A EDP CP

Constant Yield Lines 99% yield line CP (Upsized) CLB: 10x CP Sense Amp: 2x CP EDP CP CMOS TG CP Upsized EDP Yield B = Yield A A B

Constant Yield Lines CBL 99% line A B CBL (Upsized) CBL Yield B = Yield A EDP CBL CMOS TG CBL CP Upsized EDP

Constant Yield Lines DCVSL-SA 99% line A B DCVSL-SA (Upsized) DCVSL-SA Yield B = Yield A EDP CMOS TG CBL CP DCVSL-SA Upsized EDP

EDP and Yield CMOS TG CBL CP DCVSL-SA EDP (w/o sizing for yield) CMOS TG CBL CP DCVSL-SA EDP (constant yield)

EDP and Yield CMOS TG CBL CP DCVSL-SA EDP (w/o sizing for yield) CMOS TG CBL CP DCVSL-SA EDP (constant yield) High Voltage Space

DCVSL-SA best performing SA, and competitive with current TG and CMOS implementations. However… More difficult to design –Analog-like design process Less versatile –Mandatory latch at the output –DVS Higher design risk –6  unacceptable Summary of Results CMOS TG CBL CP DCVSL-SA EDP (constant yield) CMOS TG CBL CP DCVSL-SA Leakage Current

Summary of Results DCVSL-SA best performing SA, and competitive with current TG and CMOS implementations. However… More difficult to design –Analog-like design process Less versatile –Mandatory latch at the output –DVS Higher design risk –6  unacceptable

Sense Amplifiers in Future Technologies Design of Sense Amplifiers in the future will become more challenging. –Impact of process variations will become more pronounced –V DD will continue to scale  V SA /V DD increases  V TH /V DD increases The useful design space will be limited. –Low leakage environments –High voltage, low energy space

Thank you

Design Considerations in CLBs for Deep Sub-Micron Technologies Louis Alarcon Octavian Florescu

Energy – Delay CMOS TG CBL CP DCVSL-SA CBL CP DCVSL-SA

Low Threshold Voltage CMOS TG CBL CP DCVSL-SA