Techniques and Algorithms for Fault Grading of FPGA Interconnect Test Configurations Mehdi Baradaran Tahoori and Subhasish Mitra IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems Laboratory of Reliable Computing Department of Electrical Engineering National Tsing Hua University Hsinchu, Taiwan

2004/3/25Yen-Lin Peng 2 Outline  Introduction  FPGA model  Interconnect fault model  Previous work  Testing for opens  Testing for shorts  Algorithms and implementation details  Generalization for arbitrary logic  Results  Summary and Conclusion

2004/3/25Yen-Lin Peng 3 Introduction  Almost 80% of transistors in an FPGA are programmable switches and buffers  In order to test an FPGA, it needs test configurations and test vectors  The objective of this paper is to develop techniques to calculate fault coverage for a given set of test patterns  Switch- and gate-level fault simulation and fault- emulation technique are too time consuming  CLBs are configured as transparent logic

2004/3/25Yen-Lin Peng 4 FPGA model

2004/3/25Yen-Lin Peng 5 Interconnect Fault Model  The stuck-at faults can be modeled as shorts to VDD and ground lines  Fault list consists of  All line segments and PIP stuck-opens faults  The bridging fault of all connectable pair and possible nonconnectable pair

2004/3/25Yen-Lin Peng 6 Previous Work (1)  Fault emulation  The test configuration is modified to obtain a faulty configuration and then test vectors are applied  It is very time consuming  Needs whole test configurations and test vectors  Unable to deal with shorts between lines which cannot be directly connected

2004/3/25Yen-Lin Peng 7 Previous Work (2)  Fault simulation  Switch-level fault simulation  Due to the very large number of transistors in the FPGA, this method takes too much time  Gate-level fault simulation  All interconnect and routing details are eliminated and only gate-to-gate connectivity information is preserved

2004/3/25Yen-Lin Peng 8 Testing for Opens (1)  Used and neighbor sets  Open detection in switch matrices  Multiple independent paths  Detectable and undetectable stuck-open faults

2004/3/25Yen-Lin Peng 9 Testing for Opens (2)  Modeling of opens in line segments  Extension to the Entire FPGA

2004/3/25Yen-Lin Peng 10 Testing for Shorts (1)  Stuck-closed PIP detection in switch matrices  Detectable and undetectable stuck-closed faults

2004/3/25Yen-Lin Peng 11 Testing for Shorts (2)  Short detection in the entire FPGA  The bridging fault between two routing resources, A and B, is detectable if  A and B are a connectable pair via a PIP(P)  P is in the neighbor set  P stuck-closed fault is detectable  A and B belong to different unrelated nets  Bridging faults in nonconnectable pairs  Inductive fault analysis tools  candidate list

2004/3/25Yen-Lin Peng 12 Flowchart for Fault Coverage Calculation

2004/3/25Yen-Lin Peng 13 Algorithms and Implementation Details  LUTs are configured as transparent logic  The test configurations are converted to the appropriate graph models  Switch matrices point are translated to nodes of graph  PIPs and line segments are converted to graph edges

2004/3/25Yen-Lin Peng 14 Fault Coverage for Opens  Undetectable open fault  test configuration which form cycles in the graph model  Modified Depth First Search

2004/3/25Yen-Lin Peng 15 Fault Coverage for Shorts  Find-Connectables on the use set graph in order to find all connected pairs in the graph  DFS  For each neighbor set, check that if its ends are connected through a path in used set  Floyd-Warshall algorithm

2004/3/25Yen-Lin Peng 16 Flowchart for The Complete Method

2004/3/25Yen-Lin Peng 17 Results  Implemented using C++  A set of 100 test configurations

2004/3/25Yen-Lin Peng 18 Summary and Conclusion  Presented a new technique to calculate the fault coverage of a set of test configurations for FPGA interconnects  This method is very fast