1 In 0.53 Ga 0.47 As MOSFETs with 5 nm channel and self-aligned source/drain by MBE regrowth Uttam Singisetti PhD Defense Aug 21, 2009 *

2 Outline Motivation: why III-V MOSFETs, target device structure Approach: self-aligned source/drain by MBE regrowth FET and contacts results Conclusion and future work

3 Why III-V MOSFETs Silicon MOSFETs: Gate oxide may limit <16 nm scaling IBM 45nm NMOS Narayan et al, VLSI 2006 * Enoki et al, EDL 1990 Alternative: In 0.53 Ga 0.47 As channel MOSFETs low m* (0.041 m o ) → high injection velocity, v inj (~ 2-3×10 7 cm/s) * → increase drive current, decreased CV/I I d / W g ~ c ox (V g -V th )v inj

4 Key challenge : high-k on III-V Dielectric goals : 0.6 nm EOT, D it 1×10 12 cm -2 eV -1, low leakage Dielectrics & approaches: Atomic layer deposition (ALD) Al 2 O 3 1 Chemical beam deposition ZrO 2 2 Molecular beam epitaxy (MBE) GGO 3 3 R.Hill et al, Device research conference, B. Shin et al, ECSSL, 12, G40, R. E. Herbert et al, APL, 95, , 2009

5 MOSFET scaling * : lateral and vertical Goal : double package density → lateral scaling L g, W g, L s/d * Rodwell, IPRM 2008 double the MOSFET speed keep constant gate control vertical scaling t ox, t qw, x j

6 Drain modulates  b (DIBL) Drain induced barrier lowering (DIBL) Gate modulates  b sub-threshold slope (S) goal >>

7 DIBL : 2-D electrostatics* * Yan et al, TED, 39, 1704, 1992 C g-ch ~  ox W g L g / t ox C d-ch ~  qw W g t qw / L g aspect ratio C g-ch / C d-ch =   =  ox L g 2 / t qw t ox  qw *  = 5-10 for long channel like sub-threshold behavior*

8 MOSFET aspect ratio constant aspect ratio: L g ↓ → t ox ↓, t qw ↓ and x j ↓ aspect ratio active region rectangle → → DIBL

9 Target device structure Target 22 nm gate length Control of short-channel effects  vertical scaling 1 nm EOT: thin gate dielectric, surface-channel device 5 nm quantum well thickness < 5 nm deep source / drain regions

10 increase I d to reduce circuit delay (  d ) ~3 mA/  m target drive current  low access resistance self-aligned, low resisitivity source / drain contacts self-aligned N+ source / drain regions with high doping InGaAs MOSFET: target drive current

11 22 nm InGaAs MOSFET: source resistance IBM High-k Metal gate transistor Image Source:EE Times LgLg L S/D Source access resistance degrades I d and g m IC Package density : L S/D ~ L g =22 nm   c must be low Need low sheet resistance in thin ~5 nm N+ layer Design targets:  c ~1  m 2,  sheet ~ 400 

12 22nm ion implanted InGaAs MOSFET Shallow junctions ( ~ 5 nm), high (~5×10 19 cm -3 ) doping Doping abruptness ( ~ 1 nm/decade) Lateral Straggle ( ~ 5 nm) Deep junctions would lead to degraded short channel effects Key Technological Challenges

13 InGaAs MOSFET with raised source/drain by regrowth 1 Wistey, EMC Baraskar, JVST 2009 Interface HAADF-STEM 1 2 nm InGaAs regrowth Self-aligned source/drain defined by MBE regrowth 1 Self-aligned in-situ Mo contacts 2 Process flow & dimensions selected for 22 nm L g design; present 200 nm gate length

14 Regrown S/D process: key features Vertical S/D doping profile set by MBE no n+ junction extension below channel abrupt on ~ 1 nm scale Self-aligned & low resistivity...source / drain N+ regions...source / drain metal contacts Gate-first gate dielectric formed after MBE growth uncontaminated / undamaged surface

15 Process flow* * Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009

16 SiO2 W Cr FIB Cross-section Damage free channel Process scalable to sub-100 nm gate lengths Key challenge in S/D process: gate stack etch Requirement: avoid damaging semiconductor surface: Approach: Gate stack with multiple selective etches * * Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009

17 Key challenge in S/D process: dielectric sidewall Simulation in Atlas, Silvaco t sw n (cm -3 ) R s (  m) 10 nm > 1× nm> 5× nm~ 4× n under sidewall → electrostatic spillover from source and gate spillover

18 Key challenge in S/D process: dielectric sidewall Sidewall must be kept thin: avoid carrier depletion, low leakage Target < 15 nm sidewall in 22 nm L g device nm SiN x thick sidewalls in present devices Pulse doping in the barrier: compensate for carrier depletion from D it

19 Surface cleaning before regrowth 30 min UV Ozone Ex-situ HCl:H 2 O clean In-situ 30 min H clean Interface HAADF-STEM * 2 nm InGaAs regrowth * Wistey, EMC 2008 c(4×2) reconstruction before regrowth → minimum process contamination TEM by Dr. J. Cagnon, Stemmer Group, UCSB MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti

20 Self-aligned contacts: height selective etching* Mo InGaAs PR * Burek et al, J.Cryst.Growth 2009 Dummy gate No regrowth

21 1 st generation MOSFETs Extremely low drive current: 2  A/  m Extremely high R on = 0.7 M  m Why is R s so high? R on ~ 0.7 M  m!

22 Source resistance : gap in Regrowth W / Cr / SiO 2 gate SEM Shadowing by gate: No regrowth next to gate Gap region is depleted of electrons High source resistance because of electron depletion in the gap MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti W/Cr gate Mo+InGaAs Ti/Au Pad Gap in regrowth SiO 2 cap

23 Migration enhanced epitaxial (MEE) regrowth* *Wistey, EMC 2008 Wistey, ICMBE 2008 High T migration enhanced Epitaxial (MEE) regrowth* regrowth interface gate No Gap 45 o tilt SEM Top of SiO 2 gate No Gap Side of gate High temperature migration enhanced epitaxial regrowth MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti

24 MEE source/drain regrowth MOSFET SEMs Cross-section after regrowth, but before Mo deposition Top view of completed device MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti

25 Regrown S/D FETs: Images Mo gate post gate

26 MOSFET characteristics Maximum Drive current ( I d ): 0.95 mA/  m Peak transconductance ( g m ): 0.37 mS  m 4.7 nm Al 2 0 3, 1×10 13 cm -2 pulse doping I d and g m below expected values

27 SEM FET source resistance Series resistance estimated by extrapolating R on to zero gate length Source access resistance ~ 500  m

28 Source resistance : regrowth TLMs W / Cr / SiO 2 gate SEM No regrowth SEM TLMs fabricated on the regrowth far away from the gate Regrowth sheet resistance ~ 29  Mo/InGaAs contact resistance ~ 5.5  m 2 (12.6  m) TLM data does not explain 500  m observed FET source resistance FET Regrowth TLMs

29 Source resistance: electron depletion near gate Electron depletion in regrowth shadow region (R 1 ) Electron depletion in the channel under SiN x sidewalls (R 2 ) R1 R2 MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti

30 SiO 2 W Cr InGaAs InAlAs Regrowth profile dependance on As flux* Uniform filling with lower As flux multiple InGaAs regrowths with InAlAs marker layers increasing As flux regrowth surface * Wistey et al, EMC 2009 Wistey et al NAMBE 2009 MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti uniform filling

31 InAs source/drain regrowth 1 Wistey et al, EMC 2009 Wistey et al NAMBE Bhargava et al, APL 1997 Improved InAs regrowth with low As flux for uniform filling 1 InAs less susceptible to electron depletion: Fermi pinning above E c 2 MBE growth by Ashish Baraskar, device fabrication and characterization by U.Singisetti InAs regrowth Gate InGaAs 100 nm

32 Regrown InAs S/D FETs Mo S/D metal with N+ InAs underneath side of gate top of gate gate Mo S/D metal with N+ InAs underneath 4.7 nm Al 2 0 3, 5×10 12 cm -2 pulse doping MBE growth by Dr. Mark Wistey, device fabrication and characterization by U.Singisetti

33 InAs S/D E-FET DC Characteristics 4.7 nm Al 2 0 3, InAs S/D E-FET

34 InAs S/D E-FET DC characteristics 4.7 nm Al 2 0 3, InAs S/D E-FET R on = 600  m 0.85 mA/  m peak I d, ~0.36 mS/  m peak g m * Singisetti et al, IEEE EDL, submitted

35 Sub-threshold characteristics I on / I off ~ 10 4 :1 High sub-threshold swing Hysteresis

36 Source-drain access resistance* R on = 600  -  m for L g =0.2  m so R s < 300  m R s is too small to explain observed g m or I d *Wistey et al, NAMBE 2009

37 Source access resistance Mo/InAs contact resistance : 3.5  m 2 (8.5  m) InAs sheet resistance: 20  Electron depletion at Al 2 O 3 /InGaAs interface under sidewall MBE growth by Ashish Baraskar, device fabrication and characterization by U.Singisetti InAs regrowth Gate InGaAs 100 nm

38 Key challenge in S/D process: dielectric sidewall Simulation in Atlas, Silvaco t sw n (cm -3 ) R s (  m) 10 nm > 1× nm> 5× nm~ 4× n under sidewall → electrostatic spillover from source and gate spillover

39 Gate dielectric D it D it from sub-threshold swing = 2 ×10 13 cm -2 eV -1 GS

40 Threshold voltaget (V t ) Expected V t = V, actual V t = 0.6 V D it = ∆ V t / qC ox = 1.5 ×10 13 cm -2 eV -1 V g = 0 V

41 Higher S in 200 nm device: DIBL ? higher sub-threshold swing for 200 nm device → is it DIBL L g / t qw = 200/5 = 40→ clearly not DIBL

42 InAs InAlAs Electron confinement under source/drain InGaAs Insufficient electron confinement under source/drain Need a AlAsSb barrier or higher p + doping in buffer EfEf

43 Self-aligned source/drain for thin channels ( ~ 5nm ) → scalable InAs Source/Drain E-FETs: R s < 300  m, peak I d = 0.85 mA/  m, peak g m = 0.36 mS/  m Device g m, I d not limited by R s Next: scale to ~50 nm L g scale sidewalls gate dielectric quality Conclusion

44 Acknowledgements Prof. Mark Rodwell, Prof. Umesh Mishra, Prof. Art Gossard, Prof. Chris Palmstrøm Dr. Mark Wistey, Dr. Seth Bank, Dr Yong-ju Lee Stemmer group: Dr Joël Cagnon McIntyre group (Stanford) : Eunji, Byungha Yuan Taur group (UCSD) : Yu Yuan Rodwell group members: Navin, Colin, Zach, Erik, Munkyo, Greg, Vibhor, Evan, Ashish Mishra group, photonics group clean-room buddies Nanofab staff: Jack, Brian, Don, Bill, Mike, Bob, Adam, Tony, Aidan, Luis MRL staff: Dr Tom Mates Friends and family