Microcomputer Buses Outline –What is a Bus? –Interfaces –Open Collector Buses –Tristate Buses –Bus Contention –Transmission Lines Goal –Understand bus basics –Understand bus analysis Reading –Microprocessor Systems Design, Clements, Ch. 10

What is a Bus? Bus functions –distribute power –distribute clocks –data transfer Standards –mechanical –electrical –protocol Challenges –cheap - use few wires –fast - over long distances –good - plug-and-play

Mechanical Interfaces Dominant cost factor Minimal performance factor Band/blade connector –gold-plated fingers on edge of PCB –push into socket with spring-loaded fingers –cheap, but unreliable, low density, board must be vertical –today used for daughter cards, e.g. memory modules Socket connector –half of socket on bus backplane, half on board –pin connections –reliable, dense, more expensive, variety of orientations –used for larger daughter cards, system bus, etc.

Electrical Interface Goal - transmit signals fast and reliably Bus drivers –convert logic level to standard electrical signal drive on bus –must avoid bus contention - driver fighting Bus receivers –receive standard signal, convert to logic level –fast, noise immune, low bus loading Bus wire transmission characteristics –ideally just a capacitor –really a messy transmission line »reflections »coupling to neighboring lines –presence/absence of cards changes characteristics

Bus Drivers/Receivers Must maintain proper voltage and current levels –V OH /V OL - output high/low voltage –V IH /V IL - input high/low voltage –I OH /I OL - output high/low current (positive means sink) –I IH /I IL - input high/low current (negative means source) DC noise immunity –high-level voltage immunity = V OH - V IH –low-level voltage immunity = V IL - V OL –the larger, the better for noise, but can reduce speed –bus drivers and receivers must agree on logic 0/1 levels

Current Levels Bus driver must be able to source/sink sufficient current –e.g. source 20 uA, sink 0.4 mA for every LS TTL input driven –maintains DC logic values Current drive must be much higher to achieve speed –driving large capacitance of bus –75 MHz, pF loads, 5V, 50% margin => 750 mA –receiver design tries to minimize capacitance –use standard receivers at card interface »shield internal card capacitance »provide standard load »but cause additional delay

Passive Drivers How to hook multiple drivers to bus –standard TTL or CMOS will fight if driving both 0 and 1 –most standard logic will burn out Solution: passive drivers –can only pull bus down –use resistor to pull bus up –open collector driver »open drain in CMOS/NMOS technology –wired OR - any driver can pull down bus to logic 0

Resistor Design Conflicting requirements –maximum value that will keep logic 1 on bus –minimum value for speed, driver sink capability Maximum –keep V OH with m drivers, n receivers »I leakage for drivers = 250 uA for LS TTL »I IL for receivers = 20 uA for LS TTL –noise margin = 0.4V »V IH = 2.0V for LS TTL => V OH = 2.4V –assume 10 drivers, 10 receivers –R max = (V cc - 2.4V)/(10*250uA+10*20uA) = 1000 ohms

Resistor Design (cont.) Minimum value –single driver must be able to achieve V OL –V OL = 0.4V for 0.4V margin since V IL = 0.4V –I IL = 0.4 mA –I OL = 16 mA –no driver leakage current –assume 10 receivers –Rmin = (V cc - V OL )/(I OL - n*I IL ) = 300 ohms Speed –assume 100 pF per driver/receiver –10 driver/receivers => 1000 pF load –delay ~ 2*R*C = us => really slow Power –128 address/data lines * 5*(5-0.4)/300 = 9.8 W –assume half of lines are high => ~5 W

Tristate Drivers Driver has three states –logic 0, logic 1, high impedance –usually inverter or buffer with extra enable line Most common type of driver Transceiver –driver pairs in opposite directions, separate enable lines –driver in one direction acts as receiver –use for bidirectional interfaces Buffer control –need to control enable of drivers –tricky for bidirectional buses –tristate unless in use

Bus Contention Static contention –only one driver in each logical state Dynamic contention –timing delays cause driver A switches on before drive B is off Example –read-after-write bus cycle –CPU had data bus drivers on for write –memory turns on data bus drivers for read Must examine logic and timing diagrams for all situations switching driver source

Bus Contention Analysis 40 MHz write to read transition –buffered AS* controls data bus drivers –can ignore receivers Analysis –t separation = delay between driver A off, driver B on –positive means no overlap –t SH - min. AS* negation time –t HL /t LH - min. high-to-low/max. low-to-high AS* buffer delay –t OFF /t ON - max. driver off/min. driver on delay –assume LS TTL –t separation = t SH - t LH - t OFF + t HL + t ON = = -4 ns –too slow, try FAST TTL –t separation = t SH - t LH - t OFF + t HL + t ON = = 12.3 ns

Transmission Lines As speeds get faster, everything becomes analog If signal rise time < 2.5*wirelength/velocity, model as transmission line –signal velocity ~5 ns/m in PCB trace –example: T r = 50 ps => trace > 0.4 cm is transmission line –if rise time > 5*propagation delay, model wire as capacitor –NOTE: Clements terminology is confusing, use the rules here Model bus as transmission lines –model as distributed or lumped R, C, L elements –signal velocity is sqrt(LC) per length »typically 30-50% of light speed »can be ns/m in heavily-loaded bus Characteristic impedance Z o = sqrt(L/C) –step voltage on input sees impedance –V/Z o current flows into line

Reflections Current in line hits terminating resistance R T –can generate a reflecting voltage pulse –reflections can be a large fraction of voltage pulse –if R T = Z o, then no reflection - a matched impedance –if no termination, reflect full voltage pulse back Reflections at both ends –voltage at end point is series of steps –causes delay and noise Termination –try to terminate transmission line with matched impedance –problem: hard to know or control bus impedance –problem: multiple termination points

Terminations PCB has Z o ~ 100 ohms –but connecting 100 ohm resistor to V dd or Gnd reduces noise margin on bus Solution –split termination to V dd and Gnd –194 ohm equivalent impedance –causes ~30% voltage reflection Active termination –use voltage regulator with termination resistors Custom bus driver chips usually include internal termination But still big headache in high-speed systems –killed the DECsystem-20/80

Bus Design Solution 1 –allow time for reflections to die away »e.g. wait extra time after signals are “valid” –use matched impedance at ends of bus »use ~100 ohms for PCB wires –lightly load bus and avoid long stubs »stub is side path at T junction –problem: hard to do in big, high-speed design Solution 2 –buy off-the-shelf bus –explains popularity of standard motherboards