7-Segment Displays VHDL Tutorial R. E. Haskell and D. M. Hanna T4: Xilinx LogiBLOX

7-Segment Decoder a-g LOW to turn on segment

library IEEE; use IEEE.std_logic_1164.all; entity seg7dec is port (q: in STD_LOGIC_VECTOR(3 downto 0); AtoG: out STD_LOGIC_VECTOR(6 downto 0)); end seg7dec; 7-Segment Decoder

architecture seg7dec_arch of seg7dec is begin process(q) begin case q is when "0000" => AtoG <= " "; when "0001" => AtoG <= " "; when "0010" => AtoG <= " "; when "0011" => AtoG <= " "; when "0100" => AtoG <= " "; when "0101" => AtoG <= " "; when "0110" => AtoG <= " "; when "0111" => AtoG <= " "; when "1000" => AtoG <= " "; when "1001" => AtoG <= " "; when "1010" => AtoG <= " "; when "1011" => AtoG <= " "; when "1100" => AtoG <= " "; when "1101" => AtoG <= " "; when "1110" => AtoG <= " "; when others => AtoG <= " "; end case; end process; end seg7dec_arch;

Digilab Board dig3dig2dig1dig4

Digilab Board – Common Anodes A4 A3 A2 A1 CA CB CC CD CE CF CG Pins

Multiplex displays

Multiplex displays

Multiplex displays

Multiplex displays

mux4 ctr2bit Acode seg7dec dig7seg dig1(3:0) dig2(3:0) dig3(3:0) dig4(3:0) clk anode(3:0) AtoG(6:0) A(4:1) Multiplex displays Asel(1:0) Aen(3:0) y1(3:0)

dig7seg entity dig7seg is port ( anode: in STD_LOGIC_VECTOR (3 downto 0); dig1: in STD_LOGIC_VECTOR (3 downto 0); dig2: in STD_LOGIC_VECTOR (3 downto 0); dig3: in STD_LOGIC_VECTOR (3 downto 0); dig4: in STD_LOGIC_VECTOR (3 downto 0); clk: in STD_LOGIC; AtoG: out STD_LOGIC_VECTOR (6 downto 0); A: out STD_LOGIC_VECTOR (4 downto 1) ); end dig7seg;

dig7seg architecture dig7seg_arch of dig7seg is signal y1: STD_LOGIC_VECTOR (3 downto 0); signal sel2: STD_LOGIC_VECTOR (1 downto 0); begin u0: ctr2bit port map (CLOCK => clk, Q_OUT => sel2); u1: mux4g port map (a => dig1, b => dig2, c => dig3, d => dig4, sel => sel2, y => y1); u2: seg7dec port map (q => y1, AtoG => AtoG); u3: Acode port map (Aen => anode, Asel => sel2, A => A); end dig7seg_arch;

ctr2bit -- A 2-bit up-counter library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity ctr2bit is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (1 downto 0) ); end ctr2bit;

ctr2bit (cont.) architecture ctr2bit_arch of ctr2bit is begin process (clk, clr) variable COUNT: STD_LOGIC_VECTOR (1 downto 0); begin if clr = '1' then q <= "00"; elsif clk'event and clk='1' then COUNT := COUNT + 1; q <= COUNT; end if; end process; end ctr2bit_arch;

library IEEE; use IEEE.std_logic_1164.all; entity Acode is port ( Aen: in STD_LOGIC_VECTOR (3 downto 0); Asel: in STD_LOGIC_VECTOR (1 downto 0); A: out STD_LOGIC_VECTOR (3 downto 0) ); end Acode; Acode

architecture Acode_arch of Acode is begin process(Aen, Asel) begin A <= "0000"; case Asel is when "00" => if Aen(0) = '1' then A <= "0001"; end if; when "01" => if Aen(1) = '1' then A <= "0010"; end if; when "10" => if Aen(2) = '1' then A <= "0100"; end if; when others => if Aen(3) = '1' then A <= "1000"; end if; end case; end process; end Acode_arch;

step_display

library IEEE; use IEEE.std_logic_1164.all; entity step_display is port ( dig1, dig2: in STD_LOGIC_VECTOR (3 downto 0); dig3, dig4: in STD_LOGIC_VECTOR (3 downto 0); step: in STD_LOGIC; clr: in STD_LOGIC; clkout: out STD_LOGIC; clrout: out STD_LOGIC; AtoG: out STD_LOGIC_VECTOR (6 downto 0); A: out STD_LOGIC_VECTOR (4 downto 1) ); end step_display;

architecture step_display_arch of step_display is signal anode: STD_LOGIC_VECTOR (3 downto 0); signal clk4: STD_LOGIC; begin anode <= "1111"; clrout <= clr; u1: dig7seg port map (anode => anode, dig4 => dig4, dig3 => dig3, dig2 => dig2, dig1 => dig1, clk => clk4, AtoG => AtoG, A => A); u2: osc_4k port map (clk => clk4); u3: debounce port map (inp => step, clk => clk4, clr => clr, outp => clkout); end step_display_arch;

T4 Lab Exercise

T4main library IEEE; use IEEE.std_logic_1164.all; entity T4main is port ( SW: in STD_LOGIC_VECTOR (1 to 8); BTN: in STD_LOGIC_VECTOR (1 to 4); LD: out STD_LOGIC_VECTOR (1 to 8); AtoG: out STD_LOGIC_VECTOR (6 downto 0); A: out STD_LOGIC_VECTOR (3 downto 0) ); end T4main;

architecture T4main_arch of T4main is signal tin, T, N, y: std_logic_vector(7 downto 0); signal clr, clk: std_logic; begin U0: mux2 port map (a =>y, b => SW, sel => SW(1), y => tin); Treg: reg port map (d => tin, load => SW(2), clr => clr, clk =>clk, q => T); Nreg: reg port map (d => T, load => SW(3), clr => clr, clk =>clk, q => N); U1: alu port map (a => T, b => N, sel => SW(4 to 5), y => y); U2: step_display port map (dig1 => T(3 downto 0), dig2 => T(7 downto 4), dig3 => N(3 downto 0), dig4 => N(7 downto 4), step => BTN(4), clr => BTN(1), clkout => clk, clrout => clr, A => A, AtoG => AtoG); LD <= SW; end T4main_arch;