Spectral Methods for Testing of Digital Circuits Doctoral Defense Nitin Yogi Dept. of ECE, Auburn University Dissertation Committee: Chair: Prof. Vishwani D. Agrawal Prof. Victor P. Nelson Prof. Adit D. Singh Prof. Charles E. Stroud Outside reader: Prof. Paul M. Swamidass June 12, 2009

Nitin Yogi - Doctoral Defense2 Outline Test challenges & primary goals of this work Spectral analysis fundamentals Contributions of this thesis  Spectral RTL Test generation  Minimization of N-model tests  Spectral TPG for BIST Conclusion

June 12, 2009Nitin Yogi - Doctoral Defense3 Manufacturing Test Challenges Effects Decreasing feature sizes Increasing design complexities Microchip Corp. NIST Advances in Microelectronic Fabrication Manufacturing Test Issues Increase in test generation complexity More specific test patterns required Higher number and more complex defects Increase in test data volume Increase in test time

June 12, 2009Nitin Yogi - Doctoral Defense4 Issues addressed Primary Goals of this Work 1. Develop an efficient test generation algorithm High fault coverage Low test generation complexity Low number of test vectors Increase in test generation complexity Increase in test data volume

June 12, 2009Nitin Yogi - Doctoral Defense5 Primary Goals of this Work 2. Develop a minimization approach for N-Model tests (multiple fault models) High test minimization capability Ability to handle diverse and custom fault models Increase in test data volume Higher number & more complex defects Issues addressed

June 12, 2009Nitin Yogi - Doctoral Defense6 Primary Goals of this Work 3. Develop a Built-In Self Test (BIST) synthesis scheme High fault coverage Low area overhead Low test application time Issues addressed More specific test patterns required Increase in test time

June 12, 2009Nitin Yogi - Doctoral Defense7 Outline Test challenges & primary goals of this work Spectral analysis fundamentals Contributions of this thesis  Spectral RTL Test generation  Minimization of N-model tests  Spectral TPG for BIST Conclusion

June 12, 2009Nitin Yogi - Doctoral Defense8 Spectral Analysis Fundamentals Basic idea: Interpret information in frequency domain Binary bit-streams converted to spectral coefficients using transforms like Hadamard, Haar, etc. Motivation: Good quality test vectors exhibit certain discernible spectral characteristics –Premise supported by findings of earlier works

June 12, 2009Nitin Yogi - Doctoral Defense9 Walsh Functions and Hadamard Matrix H(3) = Walsh functions: a complete orthogonal set of basis functions that can represent any arbitrary bit- stream. Walsh functions form the rows of a Hadamard matrix. Example of Hadamard matrix of order w0w0 w1w1 w2w2 w3w3 w4w4 w5w5 w6w6 w7w7 Walsh functions (order 3) time

June 12, 2009Nitin Yogi - Doctoral Defense10 Test Vectors and Bit-streams Circuit Under Test (CUT) Input 1 Input 2 Input 3 Input 4 Input 5 Input J Vector 1 → Vector 2 → Vector 3 → Vector 4 → Vector 5 → Vector K → Outputs Time A binary bit-stream

June 12, 2009Nitin Yogi - Doctoral Defense11 Spectral Analysis of a Bit-stream to -1 Modified bit-stream Vector 1 Vector 2 Vector 3. Input 1 Input 2. Bit-stream of Input Test vector set Original binary bit-stream

June 12, 2009Nitin Yogi - Doctoral Defense12 Spectral Analysis of a Bit-stream (cont.) Prominent spectral component Hadamard Matrix H(3) Bit stream Spectral coeffs. = Bit stream to analyze Correlating with Walsh functions by multiplying with Hadamard matrix.

June 12, 2009Nitin Yogi - Doctoral Defense13 Power Spectrum: “Interrupt” Signal* Spectral Coefficients Normalized Power Examples of essential components Examples of noise components Theoretical random noise level (1/128) * A primary input signal for PARWAN processor

June 12, 2009Nitin Yogi - Doctoral Defense14 Power Spectrum: “DataIn[5]” Signal Theoretical random noise level (1/128) Normalized Power Spectral Coefficients Examples of essential components Examples of noise components * A primary input signal for PARWAN processor

June 12, 2009Nitin Yogi - Doctoral Defense15 Power Spectrum: Random Signal Normalized Power Spectral Coefficients Theoretical random noise level (1/128)

June 12, 2009Nitin Yogi - Doctoral Defense16 Reverse Hadamard Transform Hadamard Matrix H(3)Bit-stream Spectral coeffs. ÷ 8 = to 0 Original binary bit-stream

June 12, 2009Nitin Yogi - Doctoral Defense17 Spectral Vector Generation Hadamard Matrix H(3) Bit-stream Perturbed spectral coeffs. ÷ to 0 New binary bit-stream sign = Bits changed

June 12, 2009Nitin Yogi - Doctoral Defense18 Effect of Noise Noise inserted in ATPG vectors using increasing spectral threshold (ST) values (i.e. increasing noise) No. of faults detected by original vectors More faults detected than original vectors

June 12, 2009Nitin Yogi - Doctoral Defense19 Significance of spectral properties Two types of test vectors generated –Spectrally inserted noise by eliminating spectral coefficients below a threshold –Randomly inserted noise by flipping proportion of bits randomly

June 12, 2009Nitin Yogi - Doctoral Defense20 Significance of spectral properties

June 12, 2009Nitin Yogi - Doctoral Defense21 Significance of spectral properties T-test results –h = 1 (hypothesis that the two data sets have equal means is rejected) –p = 8.85 x (probability with which both data sets will have equal values is low) Spectral noiseRandom noise Mean Std. dev Tests generated with ST=1 & ST=13 (3 sets for each)

June 12, 2009Nitin Yogi - Doctoral Defense22 Significance of spectral properties T-test results –h = 1 (hypothesis that the two data sets have equal means is rejected) –p = 1.54 x (probability with which both data sets will have equal values is low) Spectral noiseRandom noise Mean Std. dev Tests generated with ST=1, ST=13 & ST=25 (3 sets for each)

June 12, 2009Nitin Yogi - Doctoral Defense23 Outline Test challenges & primary goals of this work Spectral analysis fundamentals Contributions of this thesis  Spectral RTL Test generation  Minimization of N-model tests  Spectral TPG for BIST Conclusion

June 12, 2009Nitin Yogi - Doctoral Defense24 Spectral RTL Test Generation We propose a novel test generation algorithm using: –Register Transfer Level (RTL) information –Spectral techniques Primary goals: –Low test generation complexity –High fault coverage –Low test vector length

June 12, 2009Nitin Yogi - Doctoral Defense25 Faults Modeled for an RTL Module Combinational Logic FF Inputs Outputs RTL stuck-at fault sites A circuit is an interconnect of several RTL modules.

June 12, 2009Nitin Yogi - Doctoral Defense26 Proposed Test Generation Algorithm Determine prominent spectral components by spectral analysis Generate test vectors for RTL faults RTL circuit Generate new test vectors by spectral coeff. perturbation Step 1 Step 2 Fault simulate test vectors and compact Spectral properties Test vector set

June 12, 2009Nitin Yogi - Doctoral Defense27 Results for ITC’99 and ISCAS’89 Circuits Circuit name No. of gate- level faults RTL-ATPG spectral testsFlexTest Gate-level ATPGRandom tests Cov. (%) No. of vectors CPU (secs) Cov. (%) No. of vectors CPU (secs) No. of vectors Cov (%) b01-A b01-D b09-A b09-D b11-A b11-D b s s s5378* s s9234* s * Reset input added. N. Yogi and V. D. Agrawal, “Spectral RTL Test Generation for Gate-Level Stuck-at Faults,” in Proc. 15th IEEE Asian Test Symp., 2006, pp. 83–88.

June 12, 2009Nitin Yogi - Doctoral Defense28 Results for PARWAN Processor Circuit RTL Spectral ATPG* Gate-level ATPG* (FlexTest) Random vecs. Cov. (%) No. of vecs. CPU (secs) Cov. (%) No. of vecs. CPU (secs) Cov. (%) No. of vecs. Parwan 98.23% % %2814 Parwan (with DFT) 98.77% % %2948 *Sun Ultra 5, 256MB RAM N. Yogi and V. D. Agrawal, “Spectral RTL Test Generation for Microprocessors,” in Proc. 20 th International Conf. VLSI Design, Jan. 2007, pp. 473–478.

June 12, 2009Nitin Yogi - Doctoral Defense29 Test Coverage Distribution

June 12, 2009Nitin Yogi - Doctoral Defense30 Test Coverage Distribution

June 12, 2009Nitin Yogi - Doctoral Defense31 Outline Test challenges & primary goals of this work Spectral analysis fundamentals Contributions of this thesis  Spectral RTL Test generation  Minimization of N-model tests  Spectral TPG for BIST Conclusion

June 12, 2009Nitin Yogi - Doctoral Defense32 Multiple Fault Models N-Model tests: For a set of N given fault models, N ≥ 1, the N-model tests target detection of all faults in the superset of faults for all N fault models. Importance –Each fault model targets specific defects Sematech study (Nigh et. al. VTS’97) concluded … To detect most defects, tests for all fault models need to included. Minimization problem –Obtain minimized test set for considered fault models Take advantage of vectors detecting faults in multiple fault models –Fault simulator/ATPG handles only one fault model at a time Need for a new minimization approach

June 12, 2009Nitin Yogi - Doctoral Defense33 Multiple Fault Model Test Minimization Obtain fault dictionary by fault simulations –Determine faults detected by each vector ‘F’ faults : for all considered fault models ‘N’ vectors : generated to cover all faults ‘F’ Test minimization by Integer Linear Program (ILP) considering the test application cost –ILP formulation Set of integer variables Set of constraints Objective function –Solving the ILP assigns values to variables such that: Constraints are met Objective function is optimum

June 12, 2009Nitin Yogi - Doctoral Defense34 Combined ILP Define two [0, 1] integer variables: –{ t j, i j } – for each vector ; j = 1 to N t j = 0 : drop vector j t j = 1 : select vector j i j = 0 : no I DDQ measurement for vector j i j = 1 : measure I DDQ for vector j

June 12, 2009Nitin Yogi - Doctoral Defense35 Combined ILP (cont.) Constraints {c k } for k th fault, k = 1 to F –For k th fault detected by vectors u, v and w c k : t u + t v + t w ≥ 1 i u + i v + i w ≥ 1 t u ≥ i u t v ≥ i v t w ≥ i w Only if k th fault is an I DDQ fault

June 12, 2009Nitin Yogi - Doctoral Defense36 Combined ILP (cont.) Objective function –Minimize { ∑ t j + W × ∑ i j } N : total number of vectors t j : variables to select vectors i j : variables to select I DDQ measurements W : weighting factor, W ≥ 0 –How strongly to minimize I DDQ vectors (May depend on the relative cost of current measurement) j = 1 N N

June 12, 2009Nitin Yogi - Doctoral Defense37 Hybrid LP – ILP Approximate solution to ILP Algorithm: 1.All variables redefined as real [0,1] variables (LP model) 2.Loop : a.Solve LP b.Round variables {t j }, {i j } as follows: 1.Round to 0 if ( 0.0 < variables ≤ 0.1) 2.Round to 1 if ( 0.9 ≤ variables < 1.0) c.Exit loop if no variables are rounded 3.Reconvert variables to [0,1] integers & solve ILP

June 12, 2009Nitin Yogi - Doctoral Defense38 Conventional Test Vector Minimization CircuitType of vecs Mentor Fastscan vectors Fault Cov. (%) Un-minimizedMinimized c3540 Stuck-at I DDQ (pseudo stuck-at) Transition delay Total s5378 Stuck-at I DDQ (pseudo stuck-at) Transition delay (LOS) Transition delay (LOC) Total

June 12, 2009Nitin Yogi - Doctoral Defense39 N. Yogi and V. D. Agrawal, “N-Model Tests for VLSI Circuits,” in Proc. 40th IEEE South-eastern Symp. System Theory, Mar. 2008, pp. 242–246. Results: N-Model Test Minimization Ckt. No. of vecs. & I DDQ meas. Combined ILP model ILP solutionHybrid LP – ILP solution W = 0.1W = 1W = 10W = 0.1W = 1W = 10 Vecs / I DDQ CPU $ (s.) Vecs / I DDQ CPU $ (s.) Vecs / I DDQ CPU $ (s.) Vecs / I DDQ CPU $ (s.) Vecs / I DDQ CPU $ (s.) Vecs / I DDQ CPU $ (s.) c3540 Vecs * * * I DDQ s5378 Vecs * * I DDQ * CPU time limit of 5000 s exceeded $ SUN Sparc Ultra 10, four CPU machine with 4.0 GB RAM shared among 4 CPUs Order of magnitude reduction in CPU time CktNo. of vecs. & I DDQ meas. c3540Vecs: 404 I DDQ : 45 s5378Vecs: 750 I DDQ : 70 N-Model test minimization results: Conventional test minimization results:

June 12, 2009Nitin Yogi - Doctoral Defense40 Outline Test challenges & primary goals of this work Spectral analysis fundamentals Contributions of this thesis  Spectral RTL Test generation  Minimization of N-model tests  Spectral TPG for BIST Conclusion

June 12, 2009Nitin Yogi - Doctoral Defense41 Spectral TPG for BIST We propose a novel design methodology for a Test Pattern Generator (TPG) for Built-In Self Test (BIST) environments Primary goals: –Given pre-generated test vectors, replicate their effects in hardware –Support at-speed testing for non-scan circuits –Low area overhead –Low test application times

June 12, 2009Nitin Yogi - Doctoral Defense42 Proposed Design Methodology Determine prominent spectral components by spectral analysis Preprocess test vectors (for combinational circuits) Pre-generated test vectors BIST implementation Step 1 Step 2 Spectral properties BIST TPG gate-level netlist

June 12, 2009Nitin Yogi - Doctoral Defense43 Pre-processing of Test Vectors Pre-processing of test vectors convenient for combinational circuits –Order of application of test vectors is immaterial Method employed –Reshuffling of test vectors to enhance the spectral properties

June 12, 2009Nitin Yogi - Doctoral Defense44 Reshuffling Algorithm Input Data and Parameters: N I : No of inputs N V : No. of vectors V(1:N V,1:N I ): Test vector Set of dimensions N V x N I hd: Dimension of Hadamard matrix H: Hadamard transform matrix of dimension 2 hd x 2 hd Procedure: Vector set V appended with redundant vectors to make weighting of bit-streams of all inputs = 0.5 for i=1 to N I Perform spectral analysis on bit-stream of input i: S = V(:,i) x H; Pick the prominent spectral component Sp(i) from S Rearrange vector set V such that maximum bits in the bit-streamsof inputs 1 to i match with the picked prominent spectral components Sp(1 to i) respectively. end

June 12, 2009Nitin Yogi - Doctoral Defense45 Spectral TPG Architecture To CUT Weighted pseudo-random pattern generator Spectral component synthesizer Input 1 Input 2 Input 3 Hadamard Components To CUT Randomizer Hadamard wave generator Clock divider and holding circuit (for sequential CUTs) System clock BIST clock Weighted pseudo-random bit-streams System clock BIST clock

June 12, 2009Nitin Yogi - Doctoral Defense46 Reseeding Reseeding: Setting memory elements (flip-flops) of TPG to values such that fault detection capability of generated test vectors improves. Reseeding effectively used in earlier works for LFSRs, CARs, etc.

June 12, 2009Nitin Yogi - Doctoral Defense47 Reseeding of Spectral TPG To CUT Data from external tester Serial scan interface Parallel interface Spectral BIST / Decompressor Flip-flops BIST / Decompressor Logic Mode of operationFunction External Tester Mode (ETM)One-seed-per-test vector operation Hybrid BIST Mode (HBM)Used to generate test vectors and reseed the flip-flops occasionally

June 12, 2009Nitin Yogi - Doctoral Defense48 Outline Test challenges & primary goals of this work Spectral analysis fundamentals Contributions of this thesis  Spectral RTL Test generation  Minimization of N-model tests  Spectral TPG for BIST Results without reseeding –Results for combinational circuits –Results for sequential circuits Results with reseeding –Results for combinational circuits Conclusion

June 12, 2009Nitin Yogi - Doctoral Defense49 Spectral BIST Results and Area Overhead Circuit Random vectors Weighted Random vectors Spectral BIST ATPG Coverage (No. of vecs) c %97.86%99.81%100% (247) s15850 (combinational) 96.81%97.41%98.77%100% (530) Test coverage comparison (64000 vectors) Circuit No. of gates in circuit Spectral BISTPRPG No. of gates % Area overhead No. of gates % Area overhead c s15850 (combinational) Area overhead comparison N. Yogi and V. D. Agrawal, “BIST/Test-Decompressor Design using Combinational Test Spectrum,” in Proc. 13th VLSI Design and Test Symp., Aug

June 12, 2009Nitin Yogi - Doctoral Defense50 Test Coverage vs Number of Vectors

June 12, 2009Nitin Yogi - Doctoral Defense51 Test Coverage vs Number of Vectors

June 12, 2009Nitin Yogi - Doctoral Defense52 Outline Test challenges & primary goals of this work Spectral analysis fundamentals Contributions of this thesis  Spectral RTL Test generation  Minimization of N-model tests  Spectral TPG for BIST Results without reseeding –Results for combinational circuits –Results for sequential circuits Results with reseeding –Results for combinational circuits Conclusion

June 12, 2009Nitin Yogi - Doctoral Defense53 N. Yogi and V. D. Agrawal (2008), “Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns,” Proc. 27th IEEE Asian Test Symp., pp Hadamard BIST Results Circuit Total No. of faults Number of faults detected Flex Test ATPG 64k random vectors 64k weighted random vectors Hadamard BIST (64k vectors) Haar BIST 1 (64k vectors) s s s s s s s s S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST,” in Proc. 20th International Conf. VLSI Design, 2007, pp. 485–491. Equal or more faults detected than ATPG in 5 / 8 circuits

June 12, 2009Nitin Yogi - Doctoral Defense54 N. Yogi and V. D. Agrawal (2008), “Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns,” Proc. 27th IEEE Asian Test Symp., pp S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST,” in Proc. 20th International Conf. VLSI Design, 2007, pp. 485–491. Hadamard BIST Results Circuit Total No. of faults Number of faults detected Flex Test ATPG 64k random vectors 64k weighted random vectors Hadamard BIST (64k vectors) Haar BIST 1 (64k vectors) s s s s s s s s Maximum faults detected in 6 / 8 circuits

June 12, 2009Nitin Yogi - Doctoral Defense55 N. Yogi and V. D. Agrawal (2008), “Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns,” Proc. 27th IEEE Asian Test Symp., pp Longer BIST Sequences Circuit FlexTestHadamard BIST Fault coverage (%) No. of vectors Fault coverage (%) at 64K vectors Fault coverage (%) at 128K vectors BIST vecs. for FlexTest ATPG cov. s s (!) s s (!) s s s s ATPG fault coverage achieved in 6 / 8 circuits

June 12, 2009Nitin Yogi - Doctoral Defense56 Area Overhead Circuit No. of transistors in circuit Hadamard BISTHaar BIST 1 No. of transistors % Area overhead No. of transistors % Area overhead s s s s s s s s S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST,” in Proc. 20th International Conf. VLSI Design, 2007, pp. 485–491. Approximately similar area overheads N. Yogi and V. D. Agrawal (2008), “Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns,” Proc. 27th IEEE Asian Test Symp., pp

June 12, 2009Nitin Yogi - Doctoral Defense57 Outline Test challenges & primary goals of this work Spectral analysis fundamentals Contributions of this thesis  Spectral RTL Test generation  Minimization of N-model tests  Spectral TPG for BIST Results without reseeding –Results for combinational circuits –Results for sequential circuits Results with reseeding –Results for combinational circuits Conclusion

June 12, 2009Nitin Yogi - Doctoral Defense58 Spectral TPG Results with Reseeding Mode of test application No. of vecs./ seeds No. of inputs Test data volume (bits) No. of tester cycles No. of system clock cycles Test time (us)† Conventional (parallel) Conventional (serial) Spectral BIST ETM (parallel) ETM (serial) HBM (parallel) HBM (serial) Comparison of test data volume and test time for c7552 † assuming tester clock period T tester =10ns and on-chip system clock period T clk =1ns N. Yogi and V. D. Agrawal, “BIST/Test-Decompressor Design using Combinational Test Spectrum,” in Proc. 13th VLSI Design and Test Symp., Aug

June 12, 2009Nitin Yogi - Doctoral Defense59 Spectral TPG Results with Reseeding Mode of test application No. of vecs./ seeds No. of inputs Test data volume (bits) No. of tester cycles No. of system clock cycles Test time (us)† Conventional (parallel) Conventional (serial) Spectral BIST ETM (parallel) ETM (serial) HBM (parallel) HBM (serial) Comparison of test data volume and test time for s15850 (combinational) † assuming tester clock period T tester =10ns and on-chip system clock period T clk =1ns N. Yogi and V. D. Agrawal, “BIST/Test-Decompressor Design using Combinational Test Spectrum,” in Proc. 13th VLSI Design and Test Symp., Aug

June 12, 2009Nitin Yogi - Doctoral Defense60 Conclusion Proposed methods using spectral techniques for –Test generation using RTL information –Designing a TPG for BIST Proposed Spectral RTL test generation –Generated test vectors exhibited: High fault coverage for most circuits Low test generation complexity Moderate number of test vectors N-model test defined –Proposed an ILP-based minimization approach with high compression ratio Proposed design methodology for TPG in BIST –Generated test vectors in hardware exhibited: Equal or higher fault coverage that ATPG vectors in most circuits Higher fault coverage then existing TPGs in most circuits Moderate area overhead compared to existing TPGs High test compression capabilities

June 12, 2009Nitin Yogi - Doctoral Defense61 List of Publications N. Yogi and V. D. Agrawal, “BIST/Test-Decompressor Design using Combinational Test Spectrum,” in Proc. 13th VLSI Design and Test Symp., Aug N. Yogi and V. D. Agrawal, “Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns,” 17th Asian Test Symposium, Nov N. Yogi and V. D. Agrawal, “N-Model tests for VLSI circuits,” 40th Southeastern Symposium on System Theory, March 2008 N. Yogi and V. D. Agrawal, “Transition Delay Fault Testing of Microprocessors by Spectral Method,” in Proc. 39th IEEE Southeastern Symp. System Theory, Mar. 2007, pp. 283–287. N. Yogi and V. D. Agrawal, “Spectral RTL Test Generation for Microprocessors,” 20th Int’l Conf. on VLSI Design, Jan N. Yogi and V. D. Agrawal, “Spectral RTL Test Generation for Gate-Level Stuck-at Faults,” 15th Asian Test Symp., Nov N. Yogi and V. D. Agrawal, “Spectral Characterization of Functional Vectors for Gate-Level Fault Coverage Tests," in Proc. 9th VLSI Design and Test Symp., Aug. 2006

June 12, 2009Nitin Yogi - Doctoral Defense62 Thank you. Questions?