COE 202: Digital Logic Design Combinational Circuits Part 1

Slides:



Advertisements
Similar presentations
Combinational Circuits CS370 – Spring BCD to 7 Segment Display Controller Understanding the problem: input is a 4 bit bcd digit output is the control.
Advertisements

COE 202: Digital Logic Design Combinational Circuits Part 1
1 Combinational Logic Design&Analysis. 2 Introduction We have learned all the prerequisite material: – Truth tables and Boolean expressions describe functions.
التصميم المنطقي Second Course
Combinational Logic Design
08/07/041 CSE-221 Digital Logic Design (DLD) Lecture-8:
ENGIN112 L13: Combinational Design Procedure October 1, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 13 Combinational Design Procedure.
CS 151 Digital Systems Design Lecture 13 Combinational Design Procedure.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 3 – Combinational Logic Design Part 1 –
ECE 331 – Digital System Design Logic Circuit Design (Lecture #7)
Computer Engineering (Logic Circuits) (Karnaugh Map)
Chapter 3 Combinational Logic Design
COE 202: Digital Logic Design Combinational Circuits Part 4
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 3 – Combinational Logic Design Part 1 –
Combinational Logic Design
Overview Part 1 – Design Procedure 3-1 Design Procedure
Lecture 13 Problems (Mano)
CS 105 Digital Logic Design
Digital Logic Lecture 08 By Amr Al-Awamry. Combinational Logic 1 A combinational circuit consists of an interconnection of logic gates. Combinational.
Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Lecture 12 – Design Procedure.
Sahar Mosleh PageCalifornia State University San Marcos 1 Multiplexer, Decoder and Circuit Designing.
Chap 3. Chap 3. Combinational Logic Design. Chap Combinational Circuits l logic circuits for digital systems: combinational vs sequential l Combinational.
Dr. Ahmed El-Bialy, Dr. Sahar Fawzy Combinational Circuits Dr. Ahmed El-Bialy Dr. Sahar Fawzy.
COE 202: Digital Logic Design Combinational Circuits Part 3 Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office: Ahmad Almulhem, KFUPM.
Combinational Logic Design BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering.
Ahmad Almulhem, KFUPM 2010 COE 202: Digital Logic Design Number Systems Part 4 Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
Digital Logic Design Review Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office: Ahmad Almulhem, KFUPM 2010.
COE 202: Digital Logic Design Combinational Circuits Part 4
Module 9.  Digital logic circuits can be categorized based on the nature of their inputs either: Combinational logic circuit It consists of logic gates.
Ahmad Almulhem, KFUPM 2009 COE 202: Digital Logic Design Combinational Logic Part 2 Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
Digital Electronics Lecture 6 Combinational Logic Circuit Design.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 3 – Combinational Logic Design Part 1 –
Computer Engineering (Logic Circuits) (Karnaugh Map)
Ahmad Almulhem, KFUPM 2010 COE 202: Digital Logic Design Combinational Logic Part 3 Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Combinational Circuits Part 3
CS221: Digital Logic Design Combinational Circuits
Chapter 0 - reVieW Combinational Logic Circuit, Combinational Logic Circuit, Propagation Delay, Propagation Delay, Programmable Logic. Programmable Logic.
KFUPM COE 202: Digital Logic Design Combinational Logic Part 1 Courtesy of Dr. Ahmad Almulhem.
Chap 2. Combinational Logic Circuits
Ahmad Almulhem, KFUPM 2010 COE 202: Digital Logic Design Combinational Logic Part 4 Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
Lecture 11 Combinational Design Procedure
EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009 Combinational Circuits.
1 Chapter 4 Combinational Logic Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables,
ECE 320 Homework #3 1. Simplify the Boolean function F using the don’t care conditions d, in both S.O.P. and P.O.S. form: a) F=A’B’D’+A’CD+A’BC d=A’BC’D+ACD+AB’D’
1 CS 151: Digital Design Chapter 3: Combinational Logic Design 3-1Design Procedure CS 151: Digital Design.
CS151 Introduction to Digital Design Chapter 3: Combinational Logic Design 3-1 Design Procedure 1Created by: Ms.Amany AlSaleh.
Designing Combinational Logic Circuits
Combinational Circuits
Ahmad Almulhem, KFUPM 2009 COE 202: Digital Logic Design Combinational Logic Part 1 Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
Combinational Logic Design. 2 Combinational Circuits A combinational logic circuit has: ♦ A set of m Boolean inputs, ♦ A set of n Boolean outputs ♦ n.
Chapter 0 – Week 2 Combinational Logic Design. What have been discussed Design hierarchy –Top – down –Bottom – up CAD HDL Logic synthesis.
C OMBINATIONAL L OGIC D ESIGN 1 Eng.Maha AlGubali.
Logic Design (CE1111 ) Lecture 4 (Chapter 4) Combinational Logic Prepared by Dr. Lamiaa Elshenawy 1.
1 Combinational Logic Design.  A process with 5 steps Specification Formulation Optimization Technology mapping Verification  1 st three steps and last.
Combinational Logic Design. 2 Combinational Circuits A combinational logic circuit has: ♦ A set of m Boolean inputs, ♦ A set of n Boolean outputs ♦ n.
Combinational Design, Part 2: Procedure. 2 Topics Positive vs. negative logic Design procedure.
Lecture 1 Gunjeet kaur Dronacharya group of institutions.
CS151 Introduction to Digital Design Chapter 3: Combinational Logic Design 3-4 Verification 1Created by: Ms.Amany AlSaleh.
Combinational Circuits
Combinational Logic Design&Analysis.
Combinational Logic Design
Combinational Logic Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates,
Overview Part 1 – Design Procedure Beginning Hierarchical Design
Computer Architecture CST 250
COE 202: Digital Logic Design Combinational Logic Part 1
COE 202: Digital Logic Design Combinational Circuits Part 3
Ch 4. Combinational logic
COE 202: Digital Logic Design Combinational Logic Part 3
Combinational Circuit Design
Presentation transcript:

COE 202: Digital Logic Design Combinational Circuits Part 1 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Ahmad Almulhem, KFUPM 2010

Objectives Types of Logic Circuits Designing Combinational Circuits Sequential Designing Combinational Circuits Procedure Examples Ahmad Almulhem, KFUPM 2010

Combinational Circuits Two classes of logic circuits: Combinational Circuits Sequential Circuits A Combinational circuit consists of logic gates Output depends only on input A Sequential circuit consists of logic gates and memory Output depends on current inputs and previous ones (stored in memory) Memory defines the state of the circuit. Ahmad Almulhem, KFUPM 2010

Combinational Circuits n inputs m outputs A combinational circuit has: n Boolean inputs (1 or more), m Boolean outputs (1 or more) logic gates mapping the inputs to the outputs Ahmad Almulhem, KFUPM 2010

Designing Combinational Circuits How to design a combinational circuit? Use all the information and tools you learned Binary system, Boolean Algebra, K-Maps, etc. Follow the step-by-step procedure given next Ahmad Almulhem, KFUPM 2010

Design Procedure Specification Formulation Optimization Write a specification for the circuit if one is not already available Specify/Label input and output Formulation Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification Apply hierarchical design if appropriate Optimization Apply 2-level and multiple-level optimization (Boolean Algebra, K-Map, software) Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters Ahmad Almulhem, KFUPM 2010

Design Procedure (Cont.) Technology Mapping Map the logic diagram or netlist to the implementation technology selected (e.g. map into NANDs) Verification Verify the correctness of the final design manually or using simulation Practical Considerations: Cost of gates (Number) Maximum allowed delay Fanin/Fanout Ahmad Almulhem, KFUPM 2010

Example 1 Question: Design a circuit that has a 3-bit input and a single output (F) specified as follows: F = 0, when the input is less than (5)10 F = 1, otherwise Solution: Step 1 (Specification): Label the inputs (3 bits) as X, Y, Z X is the most significant bit, Z is the least significant bit The output (1 bit) is F: F = 1  (101)2, (110)2, (111)2 F = 0  other inputs Ahmad Almulhem, KFUPM 2010

Example 1 (cont.) Question: Design a circuit that has a 3-bit input and a single output (F) specified as follows: F = 0, when the input is less than (5)10 F = 1, otherwise Solution: Step 1 (Specification): Label the inputs (3 bits) as X, Y, Z X is the most significant bit, Z is the least significant bit The output (1 bit) is F: F = 1  (101)2, (110)2, (111)2 F = 0  other inputs Ahmad Almulhem, KFUPM 2010

Example 1 (cont.) Step 2 (Formulation) Step 3 (Optimization) Obtain Truth table Step 3 (Optimization) YZ X 00 01 11 10 X Y Z F 1 F = XZ + XY 1 0 0 0 0 0 1 1 1 Circuit Diagram X Z F X Y Ahmad Almulhem, KFUPM 2010

Example 2 Question (BCD to Excess-3 Code Converter) Code converters convert from one code to another (BCD to Excess-3 in this example) The inputs are defined by the code that is to be converted (BCD in this example) The outputs are defined by the converted code (Excess-3 in this example) Recall Excess-3 code is a decimal digit plus three converted into binary, i.e. 0 is 0011, 1 is 0100, etc. Ahmad Almulhem, KFUPM 2010

Example 2 (cont.) Step 1 (Specification) 4-bit BCD input (A,B,C,D) Excess 3 Output Decimal A B C D W X Y Z 1 2 3 4 5 6 7 8 9 10-15 All other inputs Step 1 (Specification) 4-bit BCD input (A,B,C,D) 4-bit E-3 output (W,X,Y,Z) Step 2 (Formulation) Obtain Truth table Ahmad Almulhem, KFUPM 2010

Example 2 (cont.) Step 1 (Specification) 4-bit BCD input (A,B,C,D) Excess 3 Output Decimal A B C D W X Y Z 1 2 3 4 5 6 7 8 9 10-15 All other inputs x Step 1 (Specification) 4-bit BCD input (A,B,C,D) 4-bit E-3 output (W,X,Y,Z) Step 2 (Formulation) Obtain Truth table Ahmad Almulhem, KFUPM 2010

Example 2 (cont.) Step 3 (Optimization) Ahmad Almulhem, KFUPM 2010 src: Mano’s book src: online CD Ahmad Almulhem, KFUPM 2010

Example 3 Question (BCD-to-Seven-Segment Decoder) src: Mano’s book A seven-segment display is digital readout found in electronic devices like clocks, TVs, etc. Made of seven light-emitting diodes (LED) segments; each segment is controlled separately. A BCD-to-Seven-Segment decoder is a combinational circuit Accepts a decimal digit in BCD (input) Generates appropriate outputs for the segments to display the input decimal digit (output) Ahmad Almulhem, KFUPM 2010

BCD-to-Seven-Segment Example 3 (cont.) Step 1 (Specification): 4 inputs (A, B, C, D) 7 outputs (a, b, c, d, e, f, g) a b c d e f g BCD-to-Seven-Segment Decoder A B C D Ahmad Almulhem, KFUPM 2010

Example 3 (cont.) Step 2 (Formulation) BCD Input 7 Segment Decoder Decimal A B C D a b c d e f g 1 2 3 4 5 6 7 8 9 10-15 All Other Inputs Invalid BCD codes = No Light Ahmad Almulhem, KFUPM 2010

Example 3 (cont.) Step 3 (Optimization) a b c d e f g Ahmad Almulhem, KFUPM 2010

Exercise: Draw the circuit Example 3 (cont.) Step 3 (Optimization) (cont.) a = A’C + A’BD + AB’C’ + B’C’D’ b = A’B’ + A’C’D’ + A’CD + B’C’ c = A’B + B’C’ + A’C’ + A’D d = A’CD’ + A’B’C + B’C’D’+AB’C’+A’BC’D e = A’CD’ + B’C’D’ f = A’BC’ + A’C’D’ + A’BD’ + AB’C’ g = A’CD’ + A’B’C + A’BC’ + AB’C’ Exercise: Draw the circuit Ahmad Almulhem, KFUPM 2010

Conclusion There are two types of logic circuits Design Procedure Combinational Sequential Design Procedure Specification * Formulation * Optimization * Technology Mapping Verification Examples Ahmad Almulhem, KFUPM 2010