1. Lecture 11 Combinational Design Procedure
Give qualifications of instructors:
DAP
teaching computer architecture at Berkeley since 1977
Co-athor of textbook used in class
Best known for being one of pioneers of RISC
currently author of article on future of microprocessors in SciAm Sept 1995 RY
took 152 as student, TAed 152,instructor in 152
undergrad and grad work at Berkeley
joined NextGen to design fact 80x86 microprocessors
one of architects of UltraSPARC fastest SPARC mper shipping this Fall

2. Design digital circuit from specification
Overview
Design digital circuit from specification
Digital inputs and outputs known
Need to determine logic that can transform data
Start in truth table form
Create K-map for each output based on function of inputs
Determine minimized sum-of-product representation
Draw circuit diagram
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

3. Design Procedure (Mano)
Design a circuit from a specification.
Determine number of required inputs and outputs.
Derive truth table
Obtain simplified Boolean functions
Draw logic diagram and verify correctness A 1 B C R S
S = A + B + C
R = ABC

4. Previously, we have learned…
Boolean algebra can be used to simplify expressions, but not obvious:
how to proceed at each step, or
if solution reached is minimal.
Have seen five ways to represent a function:
Boolean expression
truth table
logic circuit
minterms/maxterms
Karnaugh map

5. Combinational logic design
Use multiple representations of logic functions
Use graphical representation to assist in simplification of function.
Use concept of “don’t care” conditions.
Example - encoding BCD to seven segment display.
Similar to approach used by designers in the field.

6. BCD to Seven Segment Display
Used to display binary coded decimal (BCD) numbers using seven illuminated segments.
BCD uses 0’s and 1’s to represent decimal digits Need four bits to represent required 10 digits.
Binary coded decimal (BCD) represents each decimal digit with four bits a b c g e d f

7. BCD to seven segment display
List the segments that should be illuminated for each digit.
0 a,b,c,d,e,f
1 b,c
2 a,b,d,e,g
3 a,b,c,d,g
4 b,c,f,g
5 a,c,d,f,g
6 a,c,d,e,f,g
7 a,b,c
8 a,b,c,d,e,f,g
9 a,b,c,d,f,g a b c g e d f

8. BCD to seven segment display
Derive the truth table for the circuit.
Each output column in one circuit.
Inputs
Outputs
Dec w x y z a b c d e . 1 1 1 1 1 . 1 1 1 1 . 2 1 1 1 1 1 . × × × × × × × × × × . 7 1 1 1 1 1 1 . 8 1 1 1 1 1 1 . 9 1 1 1 1 1 1 .

9. BCD to seven segment display
Find minimal sum-of-products representation for each output 1 yz wx 10 11 01 00
For segment “a” :
Note: Have only filled in ten squares, corresponding to the ten numerical digits we wish to represent.

10. Don’t care conditions (BCD display) ...
Fill in don’t cares for undefined outputs.
Note that these combinations of inputs should never happen.
Leads to a reduced implementation 1 X yz wx 10 11 01 00
For segment “a” :
Put in “X” (don’t care), and interpret as either 1 or 0 as desired ….

11. Don’t care conditions (BCD display) ...
Circle biggest group of 1’s and Don’t Cares.
Leads to a reduced implementation
For segment “a” : 1 X yz wx 10 11 01 00

12. Don’t care conditions (BCD display)
Circle biggest group of 1’s and Don’t Cares.
Leads to a reduced implementation
For segment “a” : 1 X yz wx 10 11 01 00

13. Don’t care conditions (BCD display) ...
Circle biggest group of 1’s and Don’t Cares.
All 1’s should be covered by at least one implicant
For segment “a” : 1 X yz wx 10 11 01 00 yz 00 01 11 10 wx 00 1 1 1 01 1 1 1 11 X X X X 10 1 1 X X

14. Don’t care conditions (BCD display) ...
Put all the terms together
Generate the circuit
For segment “a” : 1 X yz wx 10 11 01 00

16. BCD to seven segment display
Derive the truth table for the circuit.
Each output column in one circuit.
Inputs
Outputs
Dec w x y z a b c d e . 1 1 1 1 1 . 1 1 1 1 . 2 1 1 1 1 1 . × × × × × × × × × × . 7 1 1 1 1 1 1 . 8 1 1 1 1 1 1 . 9 1 1 1 1 1 1 .

17. BCD to seven segment display
Find minimal sum-of-products representation for each output 1 yz wx 10 11 01 00
For segment “b” :

18. 1 yz wx 10 11 01 00
For segment “b” : X X X X X X

19. 1 yz wx 10 11 01 00
For segment “b” : X X X X X X

20. 1 yz wx 10 11 01 00
For segment “b” : X X X X X X

21. 1 yz wx 10 11 01 00
For segment “b” : X X X X X X

22. 1 yz wx 10 11 01 00
For segment “b” : X X X X X X

23. BCD-to-Excess-3 Code converter
BCD is a code for the decimal digits 0-9
Excess-3 is also a code for the decimal digits

24. Specification of BCD-to-Excess3
Inputs: a BCD input, A,B,C,D with A as the most significant bit and D as the least significant bit.
Outputs: an Excess-3 output W,X,Y,Z that corresponds to the BCD input.
Internal operation – circuit to do the conversion in combinational logic.

25. Formulation of BCD-to-Excess-3
Excess-3 code is easily formed by adding a binary 3 to the binary or BCD for the digit.
There are 16 possible inputs for both BCD and Excess-3.
It can be assumed that only valid BCD inputs will appear so the six combinations not used can be treated as don’t cares.

26. Optimization – BCD-to-Excess-3
Lay out K-maps for each output, W X Y Z
A step in the digital circuit design process.

27. Placing 1 on K-maps
Where are the minterms located on a K-Map?

28. Expressions for W X Y Z
W(A,B,C,D) = Σm(5,6,7,8,9) d(10,11,12,13,14,15)
X(A,B,C,D) = Σm(1,2,3,4,9) d(10,11,12,13,14,15)
Y(A,B,C,D) = Σm(0,3,4,7,8) d(10,11,12,13,14,15)
Z(A,B,C,D) = Σm(0,2,4,6,8) d(10,11,12,13,14,15)

29. Minimize K-Maps
W minimization
Find W = A + BC + BD

30. Minimize K-Maps
X minimization
Find X = BC’D’+B’C+B’D

31. Minimize K-Maps
Y minimization
Find Y = CD + C’D’

32. Minimize K-Maps
Z minimization
Find Z = D’

33. Two level circuit implementation
Have equations
W = A + BC + BD = A + B(C+D)
X = B’C + B’D + BC’D’ = B’(C+D) + BC’D’
Y = CD + C’D’
Z = D’
Factoring out (C+D) and call it T
Then T’ = (C+D)’ = C’D’
W = A + BT
X = B’T + BT’
Y = CD + T’

34. Create the digital circuit
Implementing the second set of equations where T=C+D results in a lower gate count.
This gate has a fanout of 3

35. Need to formulate circuits from problem descriptions
Summary
Need to formulate circuits from problem descriptions
Determine number of inputs and outputs
Determine truth table format
Determine K-map
Determine minimal SOP
There may be multiple outputs per design
Solve each output separately
Current approach doesn’t have memory.
This will be covered next week.
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.