Statistical Gate Delay Calculation with Crosstalk Alignment Consideration Andrew B. Kahng, Bao Liu, Xu Xu UC San Diego

Outline SSTA Background Problem formulation Method: theory and implementation Experiment Summary

Background: Variability Increased variability in nanometer VLSI designs  Process: OPC  Lgate CMP  thickness Doping  Vth  Environment: Supply voltage  transistor performance Temperature  carrier mobility  and Vth These (PVT) variations result in circuit performance variation p1p1 p2p2 PVT Parameter Distributions d1d1 d2d2 Gate/net Delay Distribution

Background: Timing Analysis Min/Max-based  Inter-die variation  Pessimistic Corner-based  Intra-die variation  Computational expensive Statistical  pdf for delays  Reports timing yield CLK DQ combinational logic FF max min

Background: SSTA Represent signal arrival times as random variables  Block-based Each timing node has an arrival time distribution Static worst case analysis Efficient for circuit optimization  Path-based Each timing node for each path has an arrival time distribution Corner-based or Monte Carlo analysis Accurate for signoff analysis B C A D I1I1 gate delay pdfs Arrival time pdf

Background: SSTA Correlations Delays and signal arrival times are random variables Correlations come from  Spatial inter-chip, intra-chip, random variations  Re-convergent fanout Multiple-input switching Cross-coupling …… corr(g1, g2) g1 g2 g3 corr(g1, g3) corr(g2, g3)

Multiple-Input Switching Simultaneous signal switching at multiple inputs of a gate leads to up to 20%(26%) gate delay mean (standard deviation) mismatch [Agarwal-Dartu- Blaauw-DAC’04] Gate delay Probability

Crosstalk Aggressor Alignment We consider an equally significant source of uncertainty in SSTA, which is crosstalk aggressor alignment induced gate delay variation MIS CAA

Problem Formulation Given  Coupled interconnect system  Gate input signal arrival time distributions Find  Gate output signal arrival time distributions We present signal arrival times in polynomial functions of normal distribution random variables E.g., for first order approximation of two input signal arrival times, their skew (crosstalk alignment) is given in normal distribution random variables with correlation taken into account x i = f i (r 1, r 2, …) r i ~ N(  i, 3  i ) x 1 ~ N(  1, 3  1 ) x 2 ~ N(  2, 3  2 ) x’=x 2 -x 1 ~ N(  ’=  2 -  1, 3  ’=3(   2 2 +corr) 1/2 )

Outline SSTA Background Problem formulation Method: theory and implementation Experiment Summary

Driver Gate Delay as a Function of Crosstalk Alignment 16X inverters driving 1000um global interconnects in 70nm technology

Driver Gate Delay as a Function of Crosstalk Alignment More complex than the timing window concept Can be computed by simulation or delay calculation Approximated in a piece-wise quadratic function:

Closed-Form Driver Gate Delay Distribution For a normal distribution crosstalk alignment x’ Transform probabilities via inverse functions

Closed-Form Driver Gate Output Signal Arrival Time Distribution For a normal distribution crosstalk alignment x’ Consider correlation via conditional probabilities

Statistical Gate Delay Calculation for Coupled Interconnect Load Input: Coupled interconnects gate input signal arrival time distributions process variations Output: Gate output signal arrival time distributions 1.Driver Gate delay calculation for sampled crosstalk alignments 2.Approximate driver gate delay in a piece-wise quadratic function of crosstalk alignment 3.Compute output signal arrival time distribution by closed-form formulas 4.Combine with other process variations

Extension to Multiple Aggressors In general, superposition does not apply for multiple aggressors because of driver output resistance variation We need to  Extract empirical functional relationships between driver gate delay and aggressors  Compute gate output signal arrival time distributions Superposition applies for long interconnects with large drivers of small output resistance

Extension to Multiple Variations Correlated variation sources  Reduce the number of variations, via PCA  Extract empirical functional relationships between gate delay and variations  Compute gate output signal arrival time distributions Independent variation sources  Applying Superposition for improved efficiency  total =  i  i  2 total =  i   i

Implementation STA-SI goes through an iteration of timing window refinement for reduced pessimism of worst case analysis SSTA-SI goes through an iteration of signal arrival time pdf refinement with reduced deviations

Runtime Analysis Driver gate delay calculation for N sampled crosstalk alignment takes O(N) time, where N = min(t 3 -t 0, 6  of crosstalk alignment) / time_step Fitting takes O(N) time Computing output signal arrival time distribution takes constant time, e.g., updating in an iterative SSTA

Outline SSTA Background Problem formulation Method: theory and implementation Experiment Summary

Experiment Setting 16X inverter drivers Coupled global interconnects in 70nm Berkeley Predictive Technology Model Extracted coupled interconnects of 451 resistors and 1637 ground and coupling capacitors in 130nm industry designs 70nmL (um)W(um)S(um)T(um) global intermediate local

Driver Gate Delay Distribution For a pair of 1000um coupled global interconnects in 70nm BPTM technology, with 10, 20, 50 and 100ps input signal transition time, and crosstalk alignment in a normal distribution N(0, 10ps)

Driver Gate Delay Standard Deviation due to Varied Gate Length For a pair of 1000um coupled global interconnects in 70nm BPTM technology, with 10, 20, 50 and 100ps input signal transition time, and wire width variation in a normal distribution N(0, 15%)

Driver Gate Delay with Gate Length and Crosstalk Alignment Variations 16X inverter drivers of coupled 70  m BPTM global interconnects 1.No variation 2.Gate length variation 3.Crosstalk alignment variation 4.Superposition results of both variations 5.SPICE results of grounding coupling capacitors and both variations 6.Our results of both variations       %65-4%54321 ’’ Tr

Driver Gate Delay with Gate Length and Crosstalk Alignment Variations Superposition of gate length and crosstalk alignment variations matches within 2.20% of SPICE Monte Carlo results Assuming no crosstalk alignment (e.g., grounding all coupling capacitors) results in 159.4%(147.4%) mismatch in mean (standard deviation) of driver gate delay variation

Driver Gate Output Signal Arrival Time Distribution For a pair of 1000  m coupled global interconnects in 70nm BPTM technology, with 10, 20, 50 and 100ps input signal transition time, and crosstalk alignment in a normal distribution N(0, 10ps)

Driver Gate Output Signal Arrival Time Distribution % diffModelSPICEModelSPICE –     3  Tr(ps) OutputDelay Test case 2: coupled interconnects in a 130nm industry design Test case 1: 1000  m interconnects of 70nm BPTM technology % diffModelSPICEModelSPICE –      3  Tr(ps) OutputDelay

Outline SSTA Background Problem formulation Method: theory and implementation Experiment Summary

SSTA must consider SI effects! We take crosstalk aggressor alignment into account in statistical gate delay calculation  We approximate driver gate delay in a piecewise quadratic function of crosstalk aggressor alignment  We derive closed-form formulas for driver gate delay and output signal arrival time distribution for given input signal arrival times in polynomial functions of normal distributions  Our experiments show that neglecting crosstalk alignment effect could lead to up to 159.4% (147.4%) mismatch of driver gate delay means (standard deviations), while our method gives output signal arrival time means (standard deviations) within 2.57% (3. 86%) of SPICE results

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