Fall 06, Sep 14 ELEC / Lecture 5 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits (Formerly ELEC / ) Dual-Threshold Low-Power Devices Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL

Fall 06, Sep 14ELEC / Lecture 52 Subthreshold Conduction V gs – V th -V ds I ds =I 0 exp( ───── ) × (1– exp ── ) nV T V T Sunthreshold slope V V gs I ds 1mA 100μA 10μA 1μA 100nA 10nA 1nA 100pA 10pA V th Subthreshold region Saturation region

Fall 06, Sep 14ELEC / Lecture 53 Thermal Voltage, v T V T = kT/q = 26 mV, at room temperature. When V ds is several times greater than V T V gs – V th I ds =I 0 exp( ───── ) nV T

Fall 06, Sep 14ELEC / Lecture 54 Leakage Current Leakage current equals I ds when V gs = 0 Leakage current equals I ds when V gs = 0 Leakage current, I ds = I 0 exp(-V th /nV T ) Leakage current, I ds = I 0 exp(-V th /nV T ) At cutoff, V gs = V th, and I ds = I 0 At cutoff, V gs = V th, and I ds = I 0 Lowering leakage to 10 -b I 0 Lowering leakage to 10 -b I 0 V th = bnV T ln 10 = 1.5b × 26 ln 10 = 90b mV Example: To lower leakage to I 0 /1,000 Example: To lower leakage to I 0 /1,000 V th = 270 mV

Fall 06, Sep 14ELEC / Lecture 55 Threshold Voltage V th = V t0 + γ[(Φ s +V sb ) ½ - Φ s ½ ] V th = V t0 + γ[(Φ s +V sb ) ½ - Φ s ½ ] V t0 is threshold voltage when source is at body potential (0.4 V for 180nm process) V t0 is threshold voltage when source is at body potential (0.4 V for 180nm process) Φ s = 2V T ln(N A /n i ) is surface potential Φ s = 2V T ln(N A /n i ) is surface potential γ = (2qε si N A ) ½ t ox /ε ox is body effect coefficient (0.4 to 1.0) γ = (2qε si N A ) ½ t ox /ε ox is body effect coefficient (0.4 to 1.0) N A is doping level = 8×10 17 cm -3 N A is doping level = 8×10 17 cm -3 n i = 1.45×10 10 cm -3 n i = 1.45×10 10 cm -3

Fall 06, Sep 14ELEC / Lecture 56 Threshold Voltage, V sb =1.1V Thermal voltage, V T = kT/q = 26 mV Thermal voltage, V T = kT/q = 26 mV Φ s = 0.93 V Φ s = 0.93 V ε ox = 3.9×8.85× F/cm ε ox = 3.9×8.85× F/cm ε si = 11.7×8.85× F/cm ε si = 11.7×8.85× F/cm t ox = 40 A o t ox = 40 A o γ = 0.6 V ½ γ = 0.6 V ½ V th = V t0 + γ[(Φ s +V sb ) ½ - Φ s ½ ] = 0.68 V V th = V t0 + γ[(Φ s +V sb ) ½ - Φ s ½ ] = 0.68 V

Fall 06, Sep 14ELEC / Lecture 57 A Sample Calculation V DD = 1.2V, 100nm CMOS process V DD = 1.2V, 100nm CMOS process Transistor width, W = 0.5μm Transistor width, W = 0.5μm OFF device (V gs = V th ) leakage OFF device (V gs = V th ) leakage I 0 = 20nA/μm, for low threshold transistor I 0 = 20nA/μm, for low threshold transistor I 0 = 3nA/μm, for high threshold transistor I 0 = 3nA/μm, for high threshold transistor 100M transistor chip 100M transistor chip Power = (100×10 6 /2)(0.5×20×10 -9 A)(1.2V) = 600mW for all low-threshold transistors Power = (100×10 6 /2)(0.5×20×10 -9 A)(1.2V) = 600mW for all low-threshold transistors Power = (100×10 6 /2)(0.5×3×10 -9 A)(1.2V) = 90mW for all high-threshold transistors Power = (100×10 6 /2)(0.5×3×10 -9 A)(1.2V) = 90mW for all high-threshold transistors

Fall 06, Sep 14ELEC / Lecture 58 Dual-Threshold Chip Low-threshold only for 20% transistors on critical path. Low-threshold only for 20% transistors on critical path. Leakage power = 600× ×0.8 Leakage power = 600× ×0.8 = = 192 mW

Fall 06, Sep 14ELEC / Lecture 59 Dual-Threshold CMOS Circuit

Fall 06, Sep 14ELEC / Lecture 510 Dual-Threshold Design To maintain performance, all gates on the critical path are assigned low V th. To maintain performance, all gates on the critical path are assigned low V th. Most of the other gates are assigned high V th. But, Most of the other gates are assigned high V th. But, Some gates on non-critical paths may also be assigned low V th to prevent those paths from becoming critical. Some gates on non-critical paths may also be assigned low V th to prevent those paths from becoming critical.

Fall 06, Sep 14ELEC / Lecture 511 Integer Linear Programming (ILP) to Minimize Leakage Power Use dual-threshold CMOS process Use dual-threshold CMOS process First, assign all gates low V th First, assign all gates low V th Use an ILP model to find the delay (T c ) of the critical path Use an ILP model to find the delay (T c ) of the critical path Use another ILP model to find the optimal V th assignment as well as the reduced leakage power for all gates without increasing T c Use another ILP model to find the optimal V th assignment as well as the reduced leakage power for all gates without increasing T c Further reduction of leakage power possible by letting T c increase Further reduction of leakage power possible by letting T c increase

Fall 06, Sep 14ELEC / Lecture 512 ILP -Variables For each gate i define two variables. T i : the longest time at which the output of gate i can produce an event after the occurrence of an input event at a primary input of the circuit. T i : the longest time at which the output of gate i can produce an event after the occurrence of an input event at a primary input of the circuit. X i : a variable specifying low or high V th for gate i ; X i is an integer [0, 1], X i : a variable specifying low or high V th for gate i ; X i is an integer [0, 1], 1  gate i is assigned low V th, 1  gate i is assigned low V th, 0  gate i is assigned high V th.

Fall 06, Sep 14ELEC / Lecture 513 ILP - objective function minimize the sum of all gate leakage currents, given by I Li is the leakage current of gate i with low V th I Li is the leakage current of gate i with low V th I Hi is the leakage current of gate i with high V th I Hi is the leakage current of gate i with high V th Using SPICE simulation results, construct a leakage current look up table, which is indexed by the gate type and the input vector. Using SPICE simulation results, construct a leakage current look up table, which is indexed by the gate type and the input vector. Leakage power:

Fall 06, Sep 14ELEC / Lecture 514 ILP - Constraints For each gate For each gate (1) (1) output of gate j is fanin of gate i (2) (2) Max delay constraints for primary outputs (PO) Max delay constraints for primary outputs (PO) (3) T max is the maximum delay of the critical path Gate j Gate i TjTj TiTi

Fall 06, Sep 14ELEC / Lecture 515 ILP Constraint Example Assume all primary input (PI) signals on the left arrive at the same time. Assume all primary input (PI) signals on the left arrive at the same time. For gate 2, constraints are For gate 2, constraints are

Fall 06, Sep 14ELEC / Lecture 516 ILP – Constraints (cont.) D Hi is the delay of gate i with high V th D Hi is the delay of gate i with high V th D Li is the delay of gate i with low V th D Li is the delay of gate i with low V th A second look-up table is constructed and specifies the delay for given gate type and fanout number. A second look-up table is constructed and specifies the delay for given gate type and fanout number.

Fall 06, Sep 14ELEC / Lecture 517 ILP – Finding Critical Delay T max can be specified or be the delay of longest path (T c ). T max can be specified or be the delay of longest path (T c ). To find T c, we change constraints (2) to an equation, assigning all gates low V th To find T c, we change constraints (2) to an equation, assigning all gates low V th Maximum T i in the ILP solution is T c. Maximum T i in the ILP solution is T c. If we replace T max with T c, the objective function minimizes leakage power without sacrificing performance. If we replace T max with T c, the objective function minimizes leakage power without sacrificing performance.

Fall 06, Sep 14ELEC / Lecture 518 Power-Delay Tradeoff If we gradually increase T max from T c, leakage power is further reduced, because more gates can be assigned high V th. If we gradually increase T max from T c, leakage power is further reduced, because more gates can be assigned high V th. But, the reduction trends to become slower. But, the reduction trends to become slower. When T max = (130%) T c, the reduction about levels off because almost all gates are assigned high V th. When T max = (130%) T c, the reduction about levels off because almost all gates are assigned high V th. Maximum leakage reduction can be 98%. Maximum leakage reduction can be 98%.

Fall 06, Sep 14ELEC / Lecture 519 Power-Delay Tradeoff

Fall 06, Sep 14ELEC / Lecture 520 Leakage Reduction Circuit Number of gates T c (ns)Unoptimized I leak (μA) Optimized (T max =T c ) LeakageReduction%Sun OS 5.7 CPU s Optimized I leak (μA) (T max =1.25T c ) Leakage Reduction %Sun OS 5.7 CPU s C C C C C C C C C C

Fall 06, Sep 14ELEC / Lecture 521 Dynamic & Leakage Power Comparison V T (thermal voltage, kT/q) and V th (threshold voltage) both depend on the temperature; leakage current also strongly depends on temperature. V T (thermal voltage, kT/q) and V th (threshold voltage) both depend on the temperature; leakage current also strongly depends on temperature. Spice simulation shows that for a 2-input NAND gate Spice simulation shows that for a 2-input NAND gate - with low V th, I 90 º C = 10 × I 27 º C - with high V th, I 90 º C = 20 × I 27 º C To manifest the projected contribution of leakage to the total power, we compare dynamic and leakage 90 º C. To manifest the projected contribution of leakage to the total power, we compare dynamic and leakage 90 º C.

Fall 06, Sep 14ELEC / Lecture 522 Dynamic & Leakage Power Comparison (cont.) Without considering glitches, the dynamic power is estimated by an event driven simulator, and is given by Without considering glitches, the dynamic power is estimated by an event driven simulator, and is given by We apply 1000 random test vectors at PIs with a vector period of 120% T c, and calculate the total number of weighted (by node capacitance) transitions in the circuit. We apply 1000 random test vectors at PIs with a vector period of 120% T c, and calculate the total number of weighted (by node capacitance) transitions in the circuit.

Fall 06, Sep 14ELEC / Lecture 523 Dynamic & Leakage o C Circuit P dyn (μW) P leak1 (μW) P leak1 / P dyn % P leak2 (μW) P leak2 / P dyn % C C C C C C C C C C

Fall 06, Sep 14ELEC / Lecture 524 Dynamic & Leakage o C Power in μW

Fall 06, Sep 14ELEC / Lecture 525 Summary Leakage power is a significant fraction of the total power in nanometer CMOS devices. Leakage power is a significant fraction of the total power in nanometer CMOS devices. Leakage power increases with temperature; can be as much as dynamic power. Leakage power increases with temperature; can be as much as dynamic power. Dual threshold design can reduce leakage. Dual threshold design can reduce leakage. Reference: Y. Lu and V. D. Agrawal, “ Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V th Assignment and Path Balancing, ” Proc. PATMOS, 2005, pp , access paper at Reference: Y. Lu and V. D. Agrawal, “ Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V th Assignment and Path Balancing, ” Proc. PATMOS, 2005, pp , access paper at