1. Leakage Power Reduction Techniques
Yuanlin Lu
ECE Dept. Auburn University
ELEC 6970

2. Outline Transistor Leakage Mechanisms Leakage Reduction techniques
- Mutli-, dual-, Variable Vth
- Dual Power Supply
- Transistor Sizing
- Transistor Stacking
- Optimal Input Vector Selection
Proposed Technique
- Using ILP to Minimize leakage
- Extend ILP to Minimize leakage and Glitch Power together
2019/4/11
ELEC 6970

3. Transistor Leakage Mechanisms
I1 - the reverse-bias pn junction leakage;
I2 - the subthreshold leakage; weak inversion conduction current between source and drain in an MOS transistor occurs when gate voltage is below Vth.
I3 - the oxide tunneling current; due to the low oxide thickness and the high electric field;
I4 - the gate current due to hot-carrier injection;
I5 - the GIDL (Gate-Induced Drain Leakage); due to high field effect in the drain junction;
I6 - the channel punchthrough current; due to the proximity of the depletion regions of the drain and the source.
I2, I5, I6 and are off-state leakage mechanisms;
I1 and I3 occur in both ON and OFF states;
I4 can occur in the off state, but more typically occurs during the transistor bias states in transition.
2019/4/11
ELEC 6970

4. Subthreshold Leakage current
u0 is the zero bias electron mobility, n is the subthreshold slope coefficient.
To decrease Subthreshold current
Cox = εox/Tox  Determined by foundry
Vgs & Vds  Vdd  dual power supply
Vth  dual-Vth, Multi-Vth, Variable Vth
W or L  gate sizing
Temperature ( VT = KT/q)
Cox is the oxide capacitance per unit area,
eox is oxide permittivity , silicon 3.9e0
tox is oxide thickness
2019/4/11
ELEC 6970

5. Outline Transistor Leakage Mechanisms Leakage Reduction techniques
- Mutli-, dual-, Variable Vth
- Dual Power Supply
- Transistor Sizing
- Transistor Stacking
- Optimal Input Vector Selection
Proposed Technique
- Using ILP to Minimize leakage
- Extend ILP to Minimize leakage and Glitch Power together
2019/4/11
ELEC 6970

6. Leakage & Delay Increasing Vth can decrease Isub exponentially
But, gate delay increase at the same time
where α models short channel effects (1.3)
When using Vth changing techniques, must
consider the tradeoff between leakage
reduction and performance reduction
Must find the value of a for a specific process um?
2019/4/11
ELEC 6970

7. MTCMOS (Multi-Threshold CMOS)
2019/4/11
ELEC 6970

8. MTCMOS (cont.) Advantage - Circuit can be modified easily
Disadvantages
- Affect delay, area
- Can only reduce leakage power in standby mode
- Not suitable for sequential circuit
2019/4/11
ELEC 6970

9. VTMOS (Variable Threshold CMOS)
Vth0 - zero-substrate-bias value for Vth
r body effect parameter
2ФF - surface potential parameter
η - Drain-induced barrier lowering (DIBL)
coefficient ( )
Using body effect, change Vth
In active mode, a zero body bias
In standby mode, a deeper reverse body bias, Vth increase
Can only reduce leakage power in standby mode
2019/4/11
ELEC 6970

10. VTMOS (cont.)
2019/4/11
ELEC 6970

11. Dual Threshold CMOS
To maintain performance, all gates on the critical path are assigned low Vth
Part of the gates on the non-critical paths are assigned high Vth
Disadvantage: Circuit structure sensitive
Advantage: Can reduce leakage power in both standby mode and active mode !
2019/4/11
ELEC 6970

12. Outline Transistor Leakage Mechanisms Leakage Reduction techniques
- Mutli-, dual-, Variable Vth
- Dual Power Supply
- Transistor Sizing
- Transistor Stacking
- Optimal Input Vector Selection
Proposed Technique
- Using ILP to Minimize leakage
- Extend ILP to Minimize leakage and Glitch Power together
2019/4/11
ELEC 6970

13. Dual Power Supply Voltages
Vdd  Isub
 gate delay
Assign Low Vdd to the gates on the non-critical path, to decrease leakage power
Assign High Vdd to the gates on the critical path, to maintain performance
Originally, for dynamic power reduction
2019/4/11
ELEC 6970

14. Outline Transistor Leakage Mechanisms Leakage Reduction techniques
- Mutli-, dual-, Variable Vth
- Dual Power Supply
- Transistor Sizing
- Transistor Stacking
- Optimal Input Vector Selection
Proposed Technique
- Using ILP to Minimize leakage
- Extend ILP to Minimize leakage and Glitch Power together
2019/4/11
ELEC 6970

15. Transistor Stacking
Serious connected ‘off’ Transistors (Transistor Stacking) can reduce leakage current greatly
When M1 and M2 are turned off, Vm at the intermediate node is positive due to small drain current.
Vgs1 < 0, reduce the subthreshold current substantially.
Vbs1 < 0, increase Vth1 (larger body effect) and thus reducing the subthreshold leakage.
Vds1 decrease, increase Vth1
Vds2 decrease, increase Vth2
Vm’s value ? reference Vm
2019/4/11
ELEC 6970

16. Outline Transistor Leakage Mechanisms Leakage Reduction techniques
- Mutli-, dual-, Variable Vth
- Dual Power Supply
- Transistor Sizing
- Transistor Stacking
- Optimal Input Vector Selection
Proposed Technique
- Using ILP to Minimize leakage
- Extend ILP to Minimize leakage and Glitch Power together
2019/4/11
ELEC 6970

17. Leakage Dependence on the Input Vector
Different Input vector, different leakage current.
00: p1 & p2 on, n1 & n2 off.
Ileak 00 = In1 + In2 = 2 * Ileak
01: n1 off. n2 is on and can be treated as shorted,
so leakage current of n1 is ignored.
p1 is on and p2 is off.
Ileak 01 = Ip2 = Ileak
10: the same as the ‘01’
Ileak 10 = Ip1 = Ileak
11: n1 & n2 on. p1 & p2 off. Due to the stacking
effect,
Ileak 11 < Ileak
So, when the input vector is ‘00’, the NOR gate has the maximal leakage current. When the input vector is ‘11’, the NOR gate has the minimum leakage current.
The leakage of a two-transistor stack is an order of magnitude less than the leakage in a single transistor
2019/4/11
ELEC 6970

18. Optimal Input Vectors Selection
There must be optimal primary input vectors which lead to the minimum leakage power in the standby mode.
For smaller ciruits
- Exhaustive Search
For larger circuits
- Random Search
- Genetic algorithm ( exploit historical information to speculate on new search points with expected improved performance to find a near-optimal solution )
Find sth about Genetic algorithm
2019/4/11
ELEC 6970

19. Outline Transistor Leakage Mechanisms Leakage Reduction techniques
- Mutli-, dual-, Variable Vth
- Dual Power Supply
- Transistor Sizing
- Transistor Stacking
- Optimal Input Vector Selection
Proposed Technique
- Using ILP to Minimize leakage
- Extend ILP to Minimize leakage and Glitch Power together
2019/4/11
ELEC 6970

20. Dual Threshold CMOS
To maintain performance, all gates on the critical path are assigned low Vth
Part of the gates on the non-critical paths are assigned high Vth, to avoid the change from non-critical path to critical path.
Disadvantage: Circuit structure sensitive
Advantage: Can reduce leakage power in both standby mode and active mode !
2019/4/11
ELEC 6970

21. Using ILP (Integer Linear Programming) to Reduce Leakage Power
In dual-threshold CMOS process
Firstly, assign all gates low Vth
Use ILP model 1 to find the delay of the critical path (Tc)
Use ILP model 2 to find the optimal Vth assignment as well as the leakage reduction of all gates without increasing Tc
Further reduce leakage power by increasing Tc
2019/4/11
ELEC 6970

22. ILP
Raja et al. [16] proposed a technique to reduce dynamic glitch power by a reduced constraint set linear program.
We modify their formulation into an integer linear program (ILP) to reduce leakage power.
ILP is a mixed ( integer value and continuous values combined together) linear programming
2019/4/11
ELEC 6970

23. ILP -Variables Each gate has two variables.
Ti: the latest time at which the output of gate i can produce an event after the occurrence of an input event at primary inputs of the circuit. Continuous value
Xi: the assignment of low or high Vth to gate i; Xi is an integer which can only be 0 or 1.
1  gate i is assigned low Vth;
0  gate i is assigned high Vth.
2019/4/11
ELEC 6970

24. ILP - objective function
- minimize the sum of all gates leakage currents, which is given by
ILi is the leakage current of gate i with low Vth;
IHi is the leakage current of gate i with high Vth;
Each gate’s leakage current can be either ILi or IHi;
Using SPICE simulation results, we constructed a leakage current look up table, which is indexed by the gate type and the input vector.
2019/4/11
ELEC 6970

25. ILP - Constraints Constraints for each gate
(1)
gate j ‘s output is gate i ‘s fan in
(2)
Max delay constraints for primary outputs (PO)
(3)
Tmax can be spec. or the delay of the critical path
2019/4/11
ELEC 6970

26. ILP – Constraints 1
assume all primary input (PI) signals on the left arrive at the same time.
For gate 2, constraints can be given by
2019/4/11
ELEC 6970

27. ILP – Constraints 1 (cont.)
DHi is the delay of gate i with high Vth;
DLi is the delay of gate i with low Vth.
A second look-up table is constructed and specifies the delay for given gate type and fanout number.
2019/4/11
ELEC 6970

28. ILP – Constraints 3
Tmax can be spec. or the delay of the critical path (Tc).
To find Tc, we change constraints 2 to a equation, which means all gates are assigned low Vth.
The maximum Ti given by AMPL CPLEX, is equal to Tc.
If we replace Tmax with Tc, the real objection function becomes minimize leakage power without sacrificing any performance.
2019/4/11
ELEC 6970

29. ILP – Constraints 3 (cont.)
If we gradually increase Tmax from the smallest value Tc, more leakage power can be reduced, because more gates on the non-critical path can be assigned high Vth.
But, the reduction trend becomes slower.
When Tmax = (130%) Tc, the reduction is saturated, because almost all the gates are assigned high Vth, and there is no more optimization space.
The maximum leakage reduction can be 98%.
Tradeoff between Leakage and Performance
2019/4/11
ELEC 6970

30. Results-Leakage Reduction
Cir.
Number of gates
Tc (ns)
Unoptimized
Ileak (μA)
Optimized
(Tmax= Tc)
Leakage
Reduction %
Sun
OS 5.7 CPU secs.
Optimized for
(Tmax=1.25Tc)
Leakage Reduction
C432
160
0.751
2.620
1.022
61.0
0.25
0.132
95.0
C499
182
0.391
4.293
3.464
19.3
0.31
0.225
94.8
0.30
C880
328
0.672
4.406
0.524
88.1
0.54
0.153
96.5
0.53
C1355
214
0.403
4.388
3.290
25.0
0.33
0.294
93.3
0.36
C1908
319
0.573
6.023
2.023
66.4
0.57
0.204
96.6
0.56
C2670
362
1.263
5.925
0.659
90.4
0.68
0.125
97.9
C3540
1097
1.748
15.622
0.972
93.8
1.71
0.319
98.0
1.70
C5315
1165
1.589
19.332
2.505
87.1
1.82
0.395
1.83
C6288
1177
2.177
23.142
6.075
73.8
2.07
0.678
97.1
2.00
C7552
1046
1.915
22.043
0.872
96.0
1.59
0.445
1.68
2019/4/11
ELEC 6970

31. Results-Dynamic & Leakage Comparison
VT (thermal voltage, kT/q) and Vth both depend on the temperature, so, leakage current also strongly depends on the temperature.
Spice simulation shows that for a 2-input NAND gate
- with low Vth, 90ºC = 10 * 27ºC
- with high Vth, 90ºC = 20 * 27ºC
To manifest the projected contribution of leakage to the total power, we compare dynamic and leakage 90ºC.
2019/4/11
ELEC 6970

32. Results-Dynamic & Leakage Comparison (cont.)
Without considering glitches, the dynamic power is estimated by an event driven simulator, and is given by
We apply 1000 random test vectors at PIs with the test period equal to (120%)Tc, and calculate the total transition No. in the circuit.
2019/4/11
ELEC 6970

33. Results-Dynamic & Leakage Comparison (cont. 2)
Circuit
Pdyn
(μW)
Pleak1
Pleak1/
Pdyn %
Pleak2
Pleak2/
Pdyn %
C432
71.17
26.20
36.8
10.22
14.3
C499
149.81
42.93
28.7
34.64
23.1
C880
135.19
44.06
32.6
5.24
3.8
C1355
162.39
43.88
27.0
32.90
20.3
C1908
185.60
60.23
33.4
20.23
10.9
C2670
92.64
59.25
64.0
6.59
7.1
C3540
218.41
156.22
71.5
9.72
4.4
C5315
299.61
193.32
64.6
25.05
8.4
C6288
215.12
231.42
108.0
60.75
28.2
C7552
229.13
220.43
96.2
8.72
2019/4/11
ELEC 6970

34. Outline Transistor Leakage Mechanisms Leakage Reduction techniques
- Mutli-, dual-, Variable Vth
- Dual Power Supply
- Transistor Sizing
- Transistor Stacking
- Optimal Input Vector Selection
Proposed Technique
- Using ILP to Minimize leakage
- Extend ILP to Minimize leakage and Glitch Power together
2019/4/11
ELEC 6970

35. Extend ILP to Minimize leakage and Glitch Power together
Fig 1. A circuit with potential glitches
Fig 3. Hazard filter effect of high Vth gates.
Three black gates are assigned high Vth.
Their delays increase accordingly.
Only two buffers are needed to eliminate all glitches due to the increased gate delay of high Vth gates.
This hazard filter effect is another advantage of dual-Vth reassignment.
Fig 2. Inserting buffers in the
circuit of Figure 1 to balance the path delays to eliminate all glitches.
2019/4/11
ELEC 6970

36. Extend ILP to Minimize leakage and Glitch Power together (cont.)
The inserted buffers for eliminating glitches consume additional leakage power, so, we may assign high Vth to them.
Most of the delay buffers are on non-critical paths and can be assigned high Vth.
For a larger circuit, the power saving due to hazard filtering would be significant while power increase due to delay buffers will be small
2019/4/11
ELEC 6970

37. Future Work
Using ILP to minimize leakage and dynamic power simultaneously.
Consider transistor sizing to reduce dynamic switching power and leakage power simultaneously.
2019/4/11
ELEC 6970

38. Thank You All !