Porting EDIF to Viva Sreesa Akella, Heather Wake, Duncan Buell, James P. Davis Department of Computer Science and Engineering, University of South Carolina MAPLD 2003 Introduction The HDL-based design methodology is time-tested and provides a very stable design flow. The EDIF netlist is generated by synthesizing a functionally working VHDL model of a design. The Star Bridge Systems Viva environment provides us the ability directly to implement this design by importing the EDIF netlist. Importing EDIF into Viva would provide the ability to implement designs previously modeled in VHDL and to obtain reference points with regard to Viva-versus VHDL performance. We have here a procedure to import successfully an EDIF netlist into the VIVA environment. Process Flow HDL Modeling Simulation using ModelSim Synthesis using Synopsys EDIF Netlist Modified EDIF netlist Viva Implementation on HC 36m Synthesis Synthesis was done using Synopsys FPGA Compiler II. The following options were set: Device:Virtex II XC2V6000 Speed:-4 Package:FF1152 Disable I/O insertion Originally Synplify was used for synthesis Certain incompatibility in the mapping of MSB ports to the MULT18x18 cells Also incompatibility of Viva environment with ports defined as arrays Shifted to FPGA Compiler II tool to avoid complications Stepwise Modifications Pick up the main cell definition and the associated sub-module cell definitions and LUTs not already defined in the Viva’s default library Modify all the Library references in the cell definitions and the associated LUT definitions to “Active_lib” (for ex: replace “libraryRef VIRTEX2” with “libraryRef Active_lib”). Modify the “view” references to “net” (for ex: replace “view and_beh” with “view net”, for all the “view” references. Modify port references to match the reference names in FPGAStrings.txt file. Importing EDIF to Viva Three ways to import modified EDIF into Viva –Place the modified cell definitions in the FPGAStrings file (bad). –Put them in a file and have the Viva object attribute EDIFFile point to it (better). –Generate a mixed FPGAStrings file and have the system’s reference this file (best). Creating the Viva object Open Viva Create signature for the component Make sure each input and output is a single bit Have the same names for the ports as in the EDIF netlist Certain important attributes need to be set while creating the Viva object System:PE5 or PE6 PE7 or PE8 Resource:CLB LibRef:top module or you can have instead EDIFFile: netlist file Setting the Viva Object Attributes The object is listed among the primitive modules defined in the selected PE. Expand the PE tree group and obtain the object. Drag this onto the sheet Tie inputs and output pins Synthesize the object Check functionality Instantiating the Viva Object Large Designs Larger and hierarchical designs pose problems. A great many modifications have to be made before the EDIF netlist is compatible with Viva. A better approach would be to break up a hierarchical design and generate netlists piece by piece. Import these individual sub module netlists into Viva and generate the top design using these sub module objects. Automating Modifications Scripts were written in Perl to perform the modifications The script takes as input the EDIF netlist and the FPGAStrings file The script performs the following modifications –Eliminates library definitions –Eliminates cells already present –Modifies cell, library and port references Design Experiments Add, subtract, multiply, divide and conquer multiply, Montgomery multiply and ECC Add modules were selected. Functional VHDL models were synthesized and the EDIF ported into Viva The models were implemented in Viva and the slice usage and timing data collected The slice usage and timing were collected for designs implemented in Viva using library objects. Design Implementation The Star Bridge Systems HC 36m system was the target platform. The HC 36m system has 7 Virtex-II chips--5 Virtex-II XC2V6000 and 2 Virtex-II XC2V4000. The building block of the architecture is the Virtex-II XC2V6000 processing element. The imported modules are instantiated into the larger Viva execution environment. Performance Results Base Units Slice Usage Hierarchical Design Slice UsageConclusions and Future Work The imported VHDL models models use fewer resources No degradation in speed Avoid re-modeling in Viva of a design that has already been modeled and tested thoroughly in HDL-methodology. Larger designs have to be imported to know the largest base level cell that could be imported without degradation in performance.