2. Copyright © 1997 Altera Corporation 11/21/2015 P.1 Compilation is too Long Danny Mok Altera HK FAE (dmok@altera.com)

3. Copyright © 1997 Altera Corporation 11/21/2015 P.2 Compilation Time

4. Copyright © 1997 Altera Corporation 11/21/2015 P.3 If you were If you were Altera Software Engineer, what shall you do ? Graphic EntryGraphic Compiler Fitting VHDL EntryVHDL Compiler Graphic processor VHDL processor AHDL Entry EDIF Entry AHDL Compiler EDIF Compiler AHDL processor EDIF processor Need different Processor for different Design Entry

5. Copyright © 1997 Altera Corporation 11/21/2015 P.4 The Other better solution Graphic EntryGraphic Compiler VHDL EntryVHDL Compiler AHDL Entry EDIF Entry AHDL Compiler EDIF Compiler Altera Internal Database Structure Fitting

6. Copyright © 1997 Altera Corporation 11/21/2015 P.5 Altera Max+Plus II Compiler Involve all different kind of Compiler e.g. AHDL, VHDL, Graphic EDIF….. Convert to Altera Internal DataBase Structure Logic Optimize e.g. Hierarchy Synthesis One-Hot State Machine Carry/Cascade Chain Multi-level Synthesis…. Partition your whole design into couple chips Fit your design within Altera device e.g. Pin lock, Implement in EAB Clique, Timing parameter Get the device timing parameter for Real time Simulation Generate the Program File to program the device e.g. SOF, POF..

7. Copyright © 1997 Altera Corporation 11/21/2015 P.6 How many time spend on each Module Most of the time spend on this TWO MODULES

8. Copyright © 1997 Altera Corporation 11/21/2015 P.7 What you can do for Netlist/Database Part Smart/Total Compiler can help –Smart Compiler if this is first time compilation, save the database result for future compilation if this is second compilation without modify of the design, this step will be skipped –Total Compiler no matter the design has been modified or not, the system will go through this step again Turn on Smart Compiler –first time need longer than Total Compiler –need more harddisk space to store the database information –subsequence will need LESS TIME than Total Compiler

9. Copyright © 1997 Altera Corporation 11/21/2015 P.8 What you can do for Logic Synthesiser Part Only turn on the Option which is useful –turn on XOR Synthesis under FLEX is useless –turn on Parallel Expanders under FLEX is useless If you design file is EDIF which is already Optimize by Synopsys –you can min. time spend on the Max+Plus II Logic Synthesizer Select the WYSIWYG –don’t forget to turn on Cascade/Carry Chain for FLEX device –don’t forget to turn on the Parallel Expanders for MAX device –you can also let Max+Plus II does further Logic Optimize for you

10. Copyright © 1997 Altera Corporation 11/21/2015 P.9 EDIF file input with different Synthesis Style

11. Copyright © 1997 Altera Corporation 11/21/2015 P.10 What you can do for Partitioner Part If your design does not need to partition to different chip, this only takes couple seconds If your design need to partition to different chip, –Max+Plus II automatic partitioning will take longer time –You can save this time by doing Manual Partition by either use Assign Device Option Physically split your design to different design file

12. Copyright © 1997 Altera Corporation 11/21/2015 P.11 What you can do for Fitter Part Basically, you can not do much on this part because this is the most valuable part of Max+Plus II Avoid to do something which is meaningless –Clique something together but actually not relate to each other –Only a portion of design need to run at high speed but tell Max+Plus II that whole chip needs to run at that high speed –Lock some pin actually the PCB does not care when the I/O pin is located For 10K device –manually assign the module to EAB is much faster than turn on Automatic Implement in EAB because Max+Plus II will try all the module one by one

13. Copyright © 1997 Altera Corporation 11/21/2015 P.12 What you can do for Timing SNF Part If you don’t need to do Real time Simulation, you can TURN OFF the Timing SNF Extractor You can Select the Function SNF Extractor if you just need to do functional test of your design –there will be no POF or SOF… file generate if this option selected Optimize Timing SNF –if you find out that the Real Time Simulation is too slow, you can turn this on (no big affect) Linked SNF Extractor –use for Board Level Simulation support both Real Time and Functional

14. Copyright © 1997 Altera Corporation 11/21/2015 P.13 What you can do for Assembler Part You can do nothing on this part, but this part only take couple seconds No big Due!!!!!!

15. Copyright © 1997 Altera Corporation 11/21/2015 P.14 More you can do Max+Plus II is very CPU and RAM demand Software Increase you CPU speed definitely can help Increase you Local RAM (64Mbytes or 128Mbytes) will good for 100K gates design Bigger the Harddisk and faster Harddisk access time will be bettter –Win95 will use Harddisk as the swap space (virtual RAM) –Bigger Usable Harddisk => bigger virtual RAM –Faster Harddisk access time => shorter virtual RAM access time RAM is more important than CPU speed –128Mbyte RAM+133Mhz CPU faster than 16Mbyte RAM+200Mhz CPU

16. Copyright © 1997 Altera Corporation 11/21/2015 P.15 OK --- But OK, I know how to save some compilation time But, when I go to the Floorplan Editor and make placement modification, Max+Plus II need to re-compile again, it take s……..o……… l……o……..n…….g time to do it Yes, you are right. Everytime you make an placement modification, Max+Plus II nee to go through –Compiler Netlist Extractor –Database Builder –Logic Synthesiser –Partitioner –Fitter –Timing SNF Extractor –Assember

17. Copyright © 1997 Altera Corporation 11/21/2015 P.16 Something you can do/Something no choice What we can do ? –Compiler Netlist Extractor –Database Builder –Logic Synthesizer –Partitioner –Fitter –Timing SNF Extractor –Assembler

18. Copyright © 1997 Altera Corporation 11/21/2015 P.17 Logic Synthesizer If you just need to control the placement, there is no point to do the Logic Synthesis again Can you turn off the Logic Synthesis ? –No. Because if you turn off the Logic Synthesis, you will get total different compilation output -- don’t forget that Max+Plus II go through the whole compilation step (including Logic Synthesis) If, there is something like…….. Design File Optimize Logic Synthesis Result Save the Optimize Logic Synthesis Result Control the Logic Cell Placement Re-compile with the Optimize Logic Synthesis Result

19. Copyright © 1997 Altera Corporation 11/21/2015 P.18 Smart Re-compiler can do this

20. Copyright © 1997 Altera Corporation 11/21/2015 P.19 If I change If I do not modify my design but only change the speed grade –Do I need to wait for S…..O……. Long again No ! –The only thing you need to do is Turn On the Smart Recompile Option –and Turn On the Maintain Current Synthesis Regardless of Device or Speed Grade Changes Option

21. Copyright © 1997 Altera Corporation 11/21/2015 P.20 Conclusion Altera Max+Plus II is a smart tool If you know what you want, you may say some of your compilation time –Turn On Smart Recompile Option –Turn the Synthesis Style to WYSIWYG –Turn On the Maintain Current Synthesis Regardless of Device or Speed Grades Changes –Turn Off the SNF Timing Extractor if you do not need Timing Simulation

22. Copyright © 1997 Altera Corporation 11/21/2015 P.21 cont... Altera Max+Plus II is the fastest FPGA/CPLD tools in the market now 420 LCELLS

23. Copyright © 1997 Altera Corporation 11/21/2015 P.22 cont.. 3500 LCELLS