1. 1 Fly – A Modifiable Hardware Compiler C. H. Ho 1, P.H.W. Leong 1, K.H. Tsoi 1, R. Ludewig 2, P. Zipf 2, A.G. Oritz 2 and M. Glesner 2 1 Department of Computer Science and Engineering The Chinese University of Hong Kong 2 Institute of Microelectronic Systems Darmstadt University of Technology, Germany

2. 2 Overview Introduction Introduction Contribution Contribution Fly Programming Language Fly Programming Language GCD Example GCD Example Floating Point extension Floating Point extension Solving Differential Equation Example Solving Differential Equation Example Discussion Discussion Conclusion Conclusion

3. 3 Introduction RTL based development method compare with software development RTL based development method compare with software development Hardware design are parallel and people think in von-Neumann patterns Hardware design are parallel and people think in von-Neumann patterns Complex in decomposing a hardware design into datapath and control Complex in decomposing a hardware design into datapath and control Hardware Interface for FPGA board must be developed Hardware Interface for FPGA board must be developed RTL based design  Low productivity RTL based design  Low productivity

4. 4 Introduction HDL address some of the issue HDL address some of the issue Higher level abstraction Higher level abstraction Translate the behavior model into RTL Translate the behavior model into RTL Fly Fly Translate the Perl-like code into VHDL Translate the Perl-like code into VHDL Open source license and easily understood and modified by other users Open source license and easily understood and modified by other users Supports a simple memory mapped interface between a host processor and FPGA Supports a simple memory mapped interface between a host processor and FPGA

5. 5 Introduction Fly support Fly support While loop While loop If – else branch If – else branch Integer arithmetic Integer arithmetic Parallel statements Parallel statements Register assignment Register assignment Fly is easily extendible Fly is easily extendible Simple FPGA – host interface readily suit for different FPGA vendor Simple FPGA – host interface readily suit for different FPGA vendor Module design make adding new arithmetic possible Module design make adding new arithmetic possible

6. 6 Fly Programming Language 6 Main Element: 6 Main Element: Assignment Assignment Parallel Statement Parallel Statement Arithmetic Expression Arithmetic Expression While Loop While Loop If-Else Branching If-Else Branching Condition Evaluation Condition Evaluation

7. 7 Compilation Technique Compilation Technique Each statement has the start and end signals Each statement has the start and end signals Construct a one-hot statement machine by cascading the signals Construct a one-hot statement machine by cascading the signals Using Perl language and a parse generator Parse::ResDescent for parsing the program for simpler and concise code Using Perl language and a parse generator Parse::ResDescent for parsing the program for simpler and concise code Output VHDL code instead of netlist Output VHDL code instead of netlist cope with many FPGA and ASIC design tools cope with many FPGA and ASIC design tools perform further logic optimization by the synthesis tools perform further logic optimization by the synthesis tools Fly Programming Language

8. 8 Main element Main element ConstructElementsExample Assignment var = expr; var1 = tempvar; Parallel statement [ {…}{…}…] [{a=b;}{b=a*c;}] Loop val op expr; Valid op: *,/,+,- a = b * c; If-else if (condition){…} else {…} if (i<=j ) {a=b;} else {a=c;} Condition expr rel expr Valid rels: >, =,==,!= i >= c

9. 9 Development Environment Fly Supports the Pilchard FPGA platform Fly Supports the Pilchard FPGA platform Pilchard use DIMM memory bus interface instead of PCI bus Pilchard use DIMM memory bus interface instead of PCI bus Less latency but Larger Bandwidth Less latency but Larger Bandwidth Using register $din[x] for transferring data and handshaking Using register $din[x] for transferring data and handshaking Porting to other FPGA platform is possible Porting to other FPGA platform is possible Transparent the whole compilation and implementation process to user by using shell script Transparent the whole compilation and implementation process to user by using shell script Host driver written by Perl and inlined C in critical sections Host driver written by Perl and inlined C in critical sections

10. 10 GCD Examples: GCD Examples:{ $s = $din[1]; $l = $din[2]; while ($s != $l) { $a = $l - $s; if ($a > 0) { $l = $a; } else { [{$s = $l;}{$l = $s;}] }} $dout[1] = $1; } Fly Programming Language

11. 11 Result A GCD coprocessor is implemented using Fly System A GCD coprocessor is implemented using Fly System Xilinx XCV300E-8 Device Xilinx XCV300E-8 Device Maximum Frequency: 126 MHz Maximum Frequency: 126 MHz Slices Used: 135 out of 3072 slices Slices Used: 135 out of 3072 slices Compute a GCD every 1.63  s (including the interface overhead) Compute a GCD every 1.63  s (including the interface overhead)

12. 12 Floating Point Extension Fly can be extended other arithmetic like floating point arithmetic Fly can be extended other arithmetic like floating point arithmetic Module library providing the floating point adder and multiplier Module library providing the floating point adder and multiplier start and end signals are added to the floating point operator start and end signals are added to the floating point operator Using block RAM as the interface to host processor Using block RAM as the interface to host processor New built-in function read_host() and write_host() New built-in function read_host() and write_host() Allow data between the host and FPGA to be buffered Allow data between the host and FPGA to be buffered Three new floating point operator “.+”, “.-” and “*” for invoking floating point operation Three new floating point operator “.+”, “.-” and “*” for invoking floating point operation Change the parser to enforce the operator precedence and instantiate the floating module appropriately Change the parser to enforce the operator precedence and instantiate the floating module appropriately

13. 13 Using modified fly compiler to solve ordinary differential equation Using modified fly compiler to solve ordinary differential equation Based on Euler method, h is step size Based on Euler method, h is step size Involving floating addition, subtraction, multiplication Involving floating addition, subtraction, multiplication Application to Solving Differential Equation

14. 14 Solving Differential Equation { $h = &read_host(1); [{$t=0.0;}{$y=1.0;}{$dy=0.0;}{onehalf=0.5;}{$index=0;}] while ($t <3.0) { [{$t = $h.* $onehalf;}{$t2 = $t.- $y;}] [{$dy = $t1.* $t2;}{$t = $t.+ $h;}] [{$y = $y.+ $dy;}{$index = $index + 1;}] $void = &write_host($y, $index); }}

15. 15 Result Using parallel statement can achieve 1.43 speedup Using parallel statement can achieve 1.43 speedup Implemented on Xilinx XCV300E-8 Device Implemented on Xilinx XCV300E-8 Device Maximum Frequency: 53.9 MHz Maximum Frequency: 53.9 MHz Slices Used: 2,349 out of 3,072 slices Slices Used: 2,349 out of 3,072 slices For h = 1/16, need 28.7us for an execution including all interface overheads For h = 1/16, need 28.7us for an execution including all interface overheads

16. 16 Discussion Fly is a flexible design Fly is a flexible design Adapt to different arithmetic by adding more library Adapt to different arithmetic by adding more library Bit parallel Arithmetic  Digit Serial Arithmetic Bit parallel Arithmetic  Digit Serial Arithmetic Fixed Point Arithmetic  Floating Point Arithmetic Fixed Point Arithmetic  Floating Point Arithmetic Fly is easy to modify for different HDL Fly is easy to modify for different HDL The grammar can be redefined The grammar can be redefined Fly enhance the productivity on building FPGA systems Fly enhance the productivity on building FPGA systems Using C-like language can significantly reduced the design time Using C-like language can significantly reduced the design time

17. 17 Conclusion Using Programming Language for FPGA design Using Programming Language for FPGA design Reuse the code Reuse the code Optimization is done by the tools Optimization is done by the tools Reduce design time Reduce design time Interface of host/FPGA is defined Interface of host/FPGA is defined Using Floating Point Arithmetic on FPGA Using Floating Point Arithmetic on FPGA Make use of high FPGA density Make use of high FPGA density More application for FPGA despite of fixed point arithmetic More application for FPGA despite of fixed point arithmetic

18. 18 Q & A