Fall 2006, Oct. 5 ELEC / Lecture 8 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Glitch-Free ASICs and Custom Design Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL

Fall 2006, Oct. 5ELEC / Lecture 82 Motivation Application Specific Integrated Circuit (ASIC) chips employ standard cell design style. Application Specific Integrated Circuit (ASIC) chips employ standard cell design style. Dynamic power consumed by glitches in a CMOS circuit, though significant, can be reduced or eliminated by design. Dynamic power consumed by glitches in a CMOS circuit, though significant, can be reduced or eliminated by design. Existing glitch reduction techniques demand customized gate design, not suitable for a standard cell ASIC. Existing glitch reduction techniques demand customized gate design, not suitable for a standard cell ASIC.

Fall 2006, Oct. 5ELEC / Lecture 83 Power Dissipation in CMOS Logic (0.25 µ ) %75%5%20 P total (0 → 1) = C L V DD 2 + t sc V DD I peak + V DD I leakage CLCL

Fall 2006, Oct. 5ELEC / Lecture 84 Prior Work: Hazard Filtering Glitch is suppressed when the inertial delay of gate exceeds the differential input delay. Glitch is suppressed when the inertial delay of gate exceeds the differential input delay. 1 or 3 2 Filtering Effect of a gate Reference: V. D. Agrawal, “Low Power Design by Hazard Filtering”, VLSI Design or 2 2

Fall 2006, Oct. 5ELEC / Lecture 85 Prior Work: A Reduced Constraint Set LP Model for Glitch Removal Satisfy glitch suppression condition at all gates: Satisfy glitch suppression condition at all gates: Differential path delay at gate input < inertial delay Use a linear program (LP) to find delays Use a linear program (LP) to find delays Path enumeration avoided Path enumeration avoided Reduced (linear) size of LP allows scalability Reduced (linear) size of LP allows scalability Design gates with specified delays Design gates with specified delays 40-60% dynamic power savings in custom design 40-60% dynamic power savings in custom design Procedure is not suitable for pre-designed cell libraries Procedure is not suitable for pre-designed cell libraries Reference: T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” VLSI Design 2003.

Fall 2006, Oct. 5ELEC / Lecture 86 Prior Work: ASIC J. M. Masgonty, S. Cserveny, C. Arm and P. D. Pfister, “Low-Power Low-Voltage Standard Cell Libraries with a Limited Number of Cells”, PATMOS ’01 J. M. Masgonty, S. Cserveny, C. Arm and P. D. Pfister, “Low-Power Low-Voltage Standard Cell Libraries with a Limited Number of Cells”, PATMOS ’01 Transistor sizing results in % savings in power Transistor sizing results in % savings in power Power optimized by minimizing parasitic capacitances Power optimized by minimizing parasitic capacitances No glitch reduction attempted No glitch reduction attempted Y. Zhang, X. Hu and D. Z. Chen, “Cell Selection from Technology Libraries for Minimizing Power”, DAC ’01 Y. Zhang, X. Hu and D. Z. Chen, “Cell Selection from Technology Libraries for Minimizing Power”, DAC ’01 Mixed Integer Linear Program (MILP) to select from different realizations of cells such that power consumption is minimized without violating delay constraints Mixed Integer Linear Program (MILP) to select from different realizations of cells such that power consumption is minimized without violating delay constraints Sum of dynamic and leakage power is minimized Sum of dynamic and leakage power is minimized Library contains cells of varying sizes, supply voltages, and threshold voltages Library contains cells of varying sizes, supply voltages, and threshold voltages Achieved 79% power saving on an average Achieved 79% power saving on an average No glitch reduction attempted. No glitch reduction attempted.

Fall 2006, Oct. 5ELEC / Lecture 87 A Glitch-Free Design Balance differential delays at cell inputs: Balance differential delays at cell inputs: Use Resistive Feedthrough cell delay elements Use Resistive Feedthrough cell delay elements Automate the design Automate the design Customized delay cell generation Customized delay cell generation Insertion into the circuit Insertion into the circuit

Fall 2006, Oct. 5ELEC / Lecture 88 Delay Elements Inverter pair: delay controlled by W/L of transistors. Inverter pair: delay controlled by W/L of transistors. Diffusion capacitor: n-diffusion, SiO2, polysilicon. Diffusion capacitor: n-diffusion, SiO2, polysilicon. Polysilicon resistor: R □ L/W Polysilicon resistor: R □ L/W Sheet resistance (0.25μ CMOS process) Sheet resistance (0.25μ CMOS process) R □ = 3.6Ω/square, with silicide R □ = 3.6Ω/square, with silicide R □ = 173.6Ω/square, with silicide masked R □ = 173.6Ω/square, with silicide masked Transmission gate Transmission gate

Fall 2006, Oct. 5ELEC / Lecture 89 Evaluation of Delay Elements

Fall 2006, Oct. 5ELEC / Lecture 810 Comparison of Delay Elements Delayelement Average delay (ns) Delay/ Power ns/μW ns/μWDelay/Area ns/grids ns/grids I II III IV II. n diffusion capacitor(2.7fF) III. Polysilicon resistor (15.4kΩ) IV. Transmission gate I. Inverter pair Resistor shows Resistor shows Maximum delay Maximum delay Minimum power and area per unit delay Minimum power and area per unit delay Hence, best delay element Hence, best delay element Resistive feed through cell Resistive feed through cell A fictitious buffer at logic level A fictitious buffer at logic level

Fall 2006, Oct. 5ELEC / Lecture 811 Resistive Feedthrough Cell A parameterized cell A parameterized cell Physical design is simple – easily automated Physical design is simple – easily automated No routing layers(M2 to M5) used – not an obstruction to the router No routing layers(M2 to M5) used – not an obstruction to the router R □ *(length of poly) Width of poly R = S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct

Fall 2006, Oct. 5ELEC / Lecture 812 RC Delay Model C L varies during transition ( model not perfectly linear) C L varies during transition ( model not perfectly linear) Spectre simulation data stored as a 3D lookup table Spectre simulation data stored as a 3D lookup table Average of signal rise and fall delays Average of signal rise and fall delays Linear interpolation used Linear interpolation used T PLH + T PHL 2 T P = Vin R CLCL Vout CLCL R TPTP

Fall 2006, Oct. 5ELEC / Lecture 813 Design Optimization Flow Design Entry Tech. Mapping Layout Remove Glitches Find delays from LP Find resistor values from lookup table Generate feed through cells and modify netlist

Fall 2006, Oct. 5ELEC / Lecture 814 Results Circuit New Standard Cell Based Design Power saved (%) in custom design Raja et al. Area overhead (%) Power saved (%) 4 bit ALU N/A c C C C C S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct

Fall 2006, Oct. 5ELEC / Lecture 815 Glitch Elimination on net86 in 4-bit ALU Source: Post layout simulation in SPECTRE

Fall 2006, Oct. 5ELEC / Lecture 816 Layouts of c880 Original layout of c880 Optimized layout of c880 Power saving = 43% Area increase= 98%

Fall 2006, Oct. 5ELEC / Lecture 817 Reference S. Uppalapati, M. L. Bushnell and V. D. Agrawal, “Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells,” Proc. 9 th VLSI Design and Test Symp., Aug , 2005, pp S. Uppalapati, M. L. Bushnell and V. D. Agrawal, “Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells,” Proc. 9 th VLSI Design and Test Symp., Aug , 2005, pp

Fall 2006, Oct. 5ELEC / Lecture 818 Conclusion Successfully devised a glitch removal method for the standard cell based design style Successfully devised a glitch removal method for the standard cell based design style Does not require redesign of the library cells Does not require redesign of the library cells Does not increase the critical path delay Does not increase the critical path delay Modified design flow maintains the benefits of ASIC Modified design flow maintains the benefits of ASIC On an average On an average Dynamic power saving: 41% Dynamic power saving: 41% Area overhead: 60% Area overhead: 60% Possible ways to reduce area overhead Possible ways to reduce area overhead Cell replacements from existing library Cell replacements from existing library On-the-fly-cell design On-the-fly-cell design Adjust routing delays for glitch suppression Adjust routing delays for glitch suppression

Fall 2006, Oct. 5ELEC / Lecture 819 Custom Design Model gates with input and output delays. Model gates with input and output delays. Gate Output delay = d Input 1 Input 2 d1 d2 Delay = d + d2 Delay = d + d1 0 ≤ d1, d2 ≤ ub

Fall 2006, Oct. 5ELEC / Lecture 820 Determination of Delays Determine the realizable upper bound (ub) on gate input differential delay by simulation of gates and delay elements. Determine the realizable upper bound (ub) on gate input differential delay by simulation of gates and delay elements. Determine input and output delays for all gates for glitch suppression. Determine input and output delays for all gates for glitch suppression. Implement gates with required delays. Implement gates with required delays. References: References: 1. T. Raja, V. D. Agrawal and M. L. Bushnell, “Design of Variable Input Delay Logic for Low Dynamic Power Circuits,” Proc. PATMOS, Sep T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay Logic and Its Application to Low Power Design,” Proc. 18 th Int’l. Conference on VLSI Design, Jan 2005, pp T. Raja, V. D. Agrawal and M. L. Bushnell, “CMOS Design of Circuits for Minimum Dynamic Power and Highest Speed,” Proc. 17 th Int’l. Conference on VLSI Design, Jan 2004, pp

Fall 2006, Oct. 5ELEC / Lecture 821 Implementation of Delays Gate delay = d+d1 VDD d1 < d2 Delay = d2-d1

Fall 2006, Oct. 5ELEC / Lecture 822 Design of c7552 Circuit Un-optimized Gate Count= 3827 Transistor Count ≈ 40,000 Critical Delay = 2.15 ns Area= 710 x 710 μm 2 Optimized Gate Count= 3828 Transistor Count ≈ 45,000 Critical Delay = 2.15 ns Area= 760 x 760 μm 2 (1.14)

Fall 2006, Oct. 5ELEC / Lecture 823 Instantaneous Power by Spice Power Saving: Peak 68%, Average 58%

Fall 2006, Oct. 5ELEC / Lecture 824 Energy Measured by Spice Energy Measured by Spice Power Saving: Average 58%