Introduction to VLSI Circuits and Systems, NCUT 2007 Chapter 12 Arithmetic Circuits in CMOS VLSI Introduction to VLSI Circuits and Systems 積體電路概論 賴秉樑 Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007

Introduction to VLSI Circuits and Systems, NCUT 2007 Outline  Bit Adder Circuits  Ripple-Carry Adders  Carry Look-Ahead Adders  Other High-Speed Adders  Multipliers

Introduction to VLSI Circuits and Systems, NCUT 2007 Half-Adder Circuits  Consider two binary digit x and y, and the binary sum is denoted by x + y such that  A half-adder has 2 inputs (x and y) and 2 outputs (the sum s and the carry-out c) Figure 12.1 Half-adder symbol and operation Figure 12.2 Half-adder logic diagram (12.1) (12.2)

Introduction to VLSI Circuits and Systems, NCUT 2007 Full-Adder Circuits  Adding n-bit binary words  In the standard carry algorithm, each of the i- th columns (i = 0, 1, 2, 3) operates according to the full-adder equation  Expressions for the network are + (12.3) + (12.4) Figure 12.4 Full-adder symbol and function table or Figure 12.3 Alternate half-adder logic networks (a) NAND2 logic (b) NOR-based network (12.5) (12.6)

Introduction to VLSI Circuits and Systems, NCUT 2007 Complementary Pass-transistor Logic  Dual-rail complementary pass-transistor logic (CPL) (12.7) (12.8) (12.9) (12.10) (12.11) (12.12) Figure 12.5 CPL full-adder design (a) 2-input array(b) Sum circuit (c) Carry circuit

Introduction to VLSI Circuits and Systems, NCUT 2007 Full-Adder Circuits (1/2) Figure 12.6 Full-adder logic networks (a) Gate-level logic(b) HA-based design Figure 12.7 AOI full-adder logic Figure 12.8 Evolution of carry-out circuit (a) Standard nFET logic (b) Mirror circuit

Introduction to VLSI Circuits and Systems, NCUT 2007 Full-Adder Circuits (2/2) Figure 12.9 Mirror AOI CMOS full-adderFigure Transmission-gate full-adder circuit

Introduction to VLSI Circuits and Systems, NCUT 2007 Outline  Bit Adder Circuits  Ripple-Carry Adders  Carry Look-Ahead Adders  Other High-Speed Adders  Multipliers

Introduction to VLSI Circuits and Systems, NCUT 2007 Ripple-Carry Adders Figure An n-bit adder Figure A 4-bit ripple-carry adder Figure Worst-case delay through the 4-bit ripple adder Figure ibt adder-subtractor circuit

Introduction to VLSI Circuits and Systems, NCUT 2007 Outline  Bit Adder Circuits  Ripple-Carry Adders  Carry Look-Ahead Adders  Other High-Speed Adders  Multipliers

Introduction to VLSI Circuits and Systems, NCUT 2007 Carry Look-Ahead Adders (1/3) Figure Basis of the carry look-ahead algorithm Figure Logic network for 4-bit CLA carry bits Figure Sum calculation using the CLA network

Introduction to VLSI Circuits and Systems, NCUT 2007 Carry Look-Ahead Adders (2/3) Figure nFET logic arrays for the CLA terms (a) C 1 logic(b) C 2 logic (c) C 3 logic(d) C 4 logic Figure Possible uses of the nFET logic arrays in Figure (a) Complementary(b) Pseudo nMOS (c) Dynamic

Introduction to VLSI Circuits and Systems, NCUT 2007 Carry Look-Ahead Adders (3/3) Figure Static CLA mirror circuit (a) Series-parallel circuit (b) Mirror equivalent Figure Static mirror circuit for C 2 Figure MODL carry circuit

Introduction to VLSI Circuits and Systems, NCUT 2007 Manchester Carry Chains Figure Propagate, generate, and carry-kill values Figure Switching network for the carry-out equation Figure Manchester circuit styles (a) Static circuit(b) Dynamic circuit Figure Dynamic Manchester carry chain

Introduction to VLSI Circuits and Systems, NCUT 2007 Extension to Wide Adders (1/2) Figure An n-bit adder network Figure bit lookahead carry generator signals Figure Block lookahead generator logic

Introduction to VLSI Circuits and Systems, NCUT 2007 Extension to Wide Adders (2/2) Figure Multilevel CLA block scheme for a 16-bit adder Figure bit CLA architecture

Introduction to VLSI Circuits and Systems, NCUT 2007 Outline  Bit Adder Circuits  Ripple-Carry Adders  Carry Look-Ahead Adders  Other High-Speed Adders  Multipliers

Introduction to VLSI Circuits and Systems, NCUT 2007 Carry-Skip Circuits Figure Carry-skip circuitry (a) Carry-skip logic (b) Generalization Figure A 16-bit adder using carry-skip circuits Figure A 2-level carry-skip adder

Introduction to VLSI Circuits and Systems, NCUT 2007 Carry-Select Adders Figure bit carry-select adder

Introduction to VLSI Circuits and Systems, NCUT 2007 Carry-Save Adders Figure Basic of a carry-save adder (a) Symbol (b) 3-to-2 reduction Figure Creation of an n-bit carry-save adder

Introduction to VLSI Circuits and Systems, NCUT 2007 Outline  Bit Adder Circuits  Ripple-Carry Adders  Carry Look-Ahead Adders  Other High-Speed Adders  Multipliers

Introduction to VLSI Circuits and Systems, NCUT 2007 Multipliers (1/2) Figure A 7-to-2 reduction using carry-save adders Figure Bit-level multiplier Figure Multiplication of two 4-bit words Figure Shift register for multiplication or division by a factor of 2

Introduction to VLSI Circuits and Systems, NCUT 2007 Multipliers (2/2) Figure Alternate view of multiplication process Figure Using a product register for multiplication Figure Shift-right multiplication sequence Figure Register-based multiplier network

Introduction to VLSI Circuits and Systems, NCUT 2007 Array Multipliers Figure An array multiplier Figure Modularized view of the multiplication sequence Figure Details for a 4 X 4 array multiplier

Introduction to VLSI Circuits and Systems, NCUT 2007 Other Multipliers Figure Clocked input registers Figure Initial cell placement for the array Figure Summary of Booth encoded digit operations