Silicon Design Page 1 The Creation of a New Computer Chip

Silicon Design Page 2 A group of people from marketing, design, applications, manufacturing and finance develop the basic concept, features and rough specifications for a new product. The Concept

Silicon Design Page 3 They all go off and work on their particular pieces of the proposal Marketing – what are the customers asking for and what will sell vs. the competition, what is the marketing plan, what will it cost Design – how will it be designed, how long will it take, what design tools will be necessary, how many people will it take, what will it cost Manufacturing – how will it be manufactured, what tooling will be necessary, how many manufacturing lines will it need, what will it cost Finance – will the product make money, what is the return on investment, what resources are available and what will need to be acquired, what will it cost

Silicon Design Page 4 They all get back together again with management and decide whether or not to proceed will the project. The Decision

Silicon Design Page 5 GO! Once the decision is made to proceed, the design team swings into action

Silicon Design Page 6 Logic Level RTL Level Transistor Level Logic Simulation Extract Parasitics & create timing model RTL Simulation Block Level Physical Layout Level – (masks) The Design Flow

Silicon Design Page 7 The Block Diagram The problem is broken down into basic functions blocks and the interfaces are specified MemoryRegisters ALUControl Branch Control Clock & Timing I/O

Silicon Design Page 8 The High Level Description The blocks are then broken down into functional units and registers. The functionality is coded in a high level descriptive language. This is known as the RTL description. operand selection and register control ALU controlmaster control IR Register File ALU

Silicon Design Page 9 The High Level Simulation The RTL description is simulated to ensure that the design performs as it should.

Silicon Design Page 10 The Logic Level Description The functional units are then broken down into logic gates and registers. This is known as the logic level description.

Silicon Design Page 11 The Logic Level Simulation The logic description is simulated to ensure that the design performs as it should. It is also compared against the RTL simulation.

Silicon Design Page 12 The Transistor Description The logic gates are broken down to their component transistors. From this description, the timing delays and electrical parasitics can be estimated. If necessary, transistors can be resized. P Field Effect Transistors N typeP type OR

Silicon Design Page 13 Field Effect Transistor Operation N type P type S D G S D G Gate = Ground = ‘0’

Silicon Design Page 14 Field Effect Transistor Operation N type P type S D G S D G Gate = Vcc = ‘1’

Silicon Design Page 15 Silicon Wafer P type substrate GND N Type Field Effect Transistor no current flow

Silicon Design Page 16 Silicon Wafer P type substrate GND Vcc N Type Field Effect Transistor

Silicon Design Page 17 Silicon Wafer P type substrate GND Vcc N Type Field Effect Transistor

Silicon Design Page 18 Silicon Wafer P type substrate GND Vcc current flow N Type Field Effect Transistor

Silicon Design Page 19 Silicon Wafer P type substrate GND Vcc P Type Field Effect Transistor no current flow VccN-Well

Silicon Design Page 20 Silicon Wafer P type substrate GND P Type Field Effect Transistor VccN-Well

Silicon Design Page 21 Silicon Wafer P type substrate GND P Type Field Effect Transistor VccN-Well

Silicon Design Page 22 Silicon Wafer P type substrate GND P Type Field Effect Transistor VccN-Well current flow

Silicon Design Page 23 Logic Gate Implementation Using Field Effect Transistors P IO P P I1I2 O PP I1 O I2 O I1 I2 O IO

Silicon Design Page 24 Silicon Wafer P type substrate Silicon Wafer P type substrate So how do we build Field Effect Transistors? We start with a blank piece of silicon wafer

Silicon Design Page 25 Silicon Wafer P type substrate Silicon Wafer P type substrate Cover it with an N-well Mask Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 26 N type dopant Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Bombard it with negatively charged ions to create the N-well

Silicon Design Page 27 Create the N-well N type dopant Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 28 Create the N-well N type dopant Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 29 Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Grow the Gate Oxide layer

Silicon Design Page 30 Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Grow the Gate Oxide layer

Silicon Design Page 31 Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Deposit Polysilicon

Silicon Design Page 32 Cover it with a Polysilicon mask Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 33 Etchant Etch the Polysilicon and Oxide Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 34 Etchant Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Etch the Polysilicon and Oxide

Silicon Design Page 35 Etchant Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Etch the Polysilicon and Oxide

Silicon Design Page 36 Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Etch the Polysilicon and Oxide

Silicon Design Page 37 Cover it with an N Transistor mask Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 38 Implant the N type Dopant Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate N type dopant

Silicon Design Page 39 Implant N Dopant Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate N type dopant

Silicon Design Page 40 Cover it with a P Transistor mask Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 41 Implant P Dopant Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate P type dopant

Silicon Design Page 42 Implant P Dopant Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate P type dopant

Silicon Design Page 43 Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Grow more Oxide

Silicon Design Page 44 Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Grow more Oxide

Silicon Design Page 45 Cover it with a Contact mask Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 46 Etch the Oxide Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Etchant

Silicon Design Page 47 Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Etchant Etch the Oxide

Silicon Design Page 48 Deposit Metal Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 49 Deposit Metal Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 50 Cover it with a Metal mask Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 51 Etch the Metal Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Etchant

Silicon Design Page 52 Etch the Metal Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Etchant

Silicon Design Page 53 Deposit Insulation Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 54 Deposit Insulation Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate Silicon Wafer P type substrate

Silicon Design Page 55 A CMOS Inverter IN OUT Gnd Vcc N-well P IO IO

Silicon Design Page 56 N-well Mask

Silicon Design Page 57 Polysilicon Mask

Silicon Design Page 58 N Transistor Mask

Silicon Design Page 59 P Transistor Mask

Silicon Design Page 60 Metal Mask

Silicon Design Page 61 Contact Mask

Silicon Design Page 62 IN OUT Gnd Vcc N-well The Completed Circuit

Silicon Design Page 63 Partial Die Plot

Silicon Design Page 64 More Partial Die Plots

Silicon Design Page 65 Complete Chip Plot Intel Microcontroller Chip – 80C196KJ

Silicon Design Page 66 Another Chip Plot

Silicon Design Page 67 Intel Pentium 4

Silicon Design Page 68 Processed Silicon Wafer

Silicon Design Page 69 Processed Silicon Wafer A wafer A die

Silicon Design Page 70 Wafer Fabrication Preceding steps done in a “wafer fab” –Silicon wafer fabrication facility Fabs are expensive –rely on high volumes to get part cost down

Silicon Design Page 71 Post-Wafer Fabrication Each die is tested to see which work Wafer is cut up –Good die are kept –Bad die are thrown away

Silicon Design Page 72 Packaging

Silicon Design Page 73 Packaging

Silicon Design Page 74 Packaging

Silicon Design Page 75 Packaging

Silicon Design Page 76 Packaging

Silicon Design Page 77 Packaging

Silicon Design Page 78 Final Testing Packaged chips are tested again –Burn-in used to eliminate infant mortality Good chips labelled and shipped