CS 61C L34 Single Cycle CPU Control I (1) Garcia, Spring 2004 © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 34 – Single Cycle CPU Control I Quake?! NBC  movie on May 3 rd. Truth stranger than fiction? “The San Andreas fault may be on the cusp of producing a flurry of quakes that could rattle SoCal w/a strong temblor every few decades or less” cnn.com/2004/TECH/science/04/14/san.andreas.awakens.ap

CS 61C L34 Single Cycle CPU Control I (2) Garcia, Spring 2004 © UCB Anatomy Review: 5 components of any Computer Personal Computer Processor Computer Control (“brain”) Datapath (“brawn”) Memory (where programs, data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk (where programs, data live when not running) Yesterday (& finish up) Today

CS 61C L34 Single Cycle CPU Control I (3) Garcia, Spring 2004 © UCB Review: How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic

CS 61C L34 Single Cycle CPU Control I (4) Garcia, Spring 2004 © UCB Register-Register Timing: One complete cycle 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers RsRtRd ALU Clk PC Rs, Rt, Rd, Op, Func ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here

CS 61C L34 Single Cycle CPU Control I (5) Garcia, Spring 2004 © UCB 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] ] 32 Result ALUct r Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs ZeroExt Mux RtRd RegDst Mux imm16 ALUSrc ALU 11 oprsrtimmediate bits16 bits5 bits rd? immediate bits Rt? Already defined 32-bit MUX; Zero Ext? What about Rt register read??

CS 61C L34 Single Cycle CPU Control I (6) Garcia, Spring 2004 © UCB 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs RtRd RegDst Extender Mux imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory 32 ALU MemWr Mu x W_Src ?? Rt?

CS 61C L34 Single Cycle CPU Control I (7) Garcia, Spring 2004 © UCB 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory MemWr ALU 32 Mu x W_Src

CS 61C L34 Single Cycle CPU Control I (8) Garcia, Spring 2004 © UCB 3f: The Branch Instruction beqrs, rt, imm16 mem[PC]Fetch the instruction from memory Equal = R[rs] == R[rt]Calculate the branch condition if (Equal) Calculate the next instruction’s address -PC = PC ( SignExt(imm16) x 4 ) else -PC = PC + 4 oprsrtimmediate bits16 bits5 bits

CS 61C L34 Single Cycle CPU Control I (9) Garcia, Spring 2004 © UCB Datapath for Branch Operations beq rs, rt, imm16 Datapath generates condition (equal) oprsrtimmediate bits16 bits5 bits 32 imm16 PC Clk 00 Adder Mux Adder 4 nPC_sel Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Equal? Cond PC Ext Inst Address Already MUX, adder, sign extend, zero

CS 61C L34 Single Cycle CPU Control I (10) Garcia, Spring 2004 © UCB Putting it All Together:A Single Cycle Datapath imm16 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction Imm16RdRtRs = Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory

CS 61C L34 Single Cycle CPU Control I (11) Garcia, Spring 2004 © UCB An Abstract View of the Implementation Data Out Clk 5 RwRaRb bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

CS 61C L34 Single Cycle CPU Control I (12) Garcia, Spring 2004 © UCB An Abstract View of the Critical Path Critical Path (Load Operation) = Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write Clk 5 RwRaRb bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address This affects how much you can overclock your PC!

CS 61C L34 Single Cycle CPU Control I (13) Garcia, Spring 2004 © UCB An Abstract View of the Implementation Data Out Clk 5 RwRaRb bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

CS 61C L34 Single Cycle CPU Control I (14) Garcia, Spring 2004 © UCB Recap: A Single Cycle Datapath Rs, Rt, Rd, Imed16 connected to datapath We have everything except control signals 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt nPC_sel

CS 61C L34 Single Cycle CPU Control I (15) Garcia, Spring 2004 © UCB Recap: Meaning of the Control Signals nPC_MUX_sel: 0  PC <– PC  PC <– PC {SignExt(Im16), 00 } Later in lecture: higher-level connection between mux and branch cond Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel PC Ext imm16 “n”=next

CS 61C L34 Single Cycle CPU Control I (16) Garcia, Spring 2004 © UCB Recap: Meaning of the Control Signals ExtOp:“zero”, “sign” ALUsrc:0  regB; 1  immed ALUctr:“add”, “sub”, “or” °MemWr:1  write memory °MemtoReg: 0  ALU; 1  Mem °RegDst:0  “rt”; 1  “rd” °RegWr:1  write register 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal =

CS 61C L34 Single Cycle CPU Control I (17) Garcia, Spring 2004 © UCB Administrivia Final Exam will be here! (2050 VLSB) Sat, , 12:30–3:30pm Take EECS Survey this week! (results will be presented to Faculty; you CAN make a difference in your education & undergraduate experience)

CS 61C L34 Single Cycle CPU Control I (18) Garcia, Spring 2004 © UCB RTL: The Add Instruction add rd, rs, rt MEM[PC]Fetch the instruction from memory R[rd] = R[rs] + R[rt]The actual operation PC = PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct bits 5 bits

CS 61C L34 Single Cycle CPU Control I (19) Garcia, Spring 2004 © UCB Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction = MEM[PC] same for all instructions PC Ext Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel imm16 Instruction

CS 61C L34 Single Cycle CPU Control I (20) Garcia, Spring 2004 © UCB The Single Cycle Datapath during Add 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 1 Extender Mux imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction R[rd] = R[rs] + R[rt] Imm16RdRsRt oprsrtrdshamtfunct nPC_sel= +4

CS 61C L34 Single Cycle CPU Control I (21) Garcia, Spring 2004 © UCB Instruction Fetch Unit at the End of Add PC = PC + 4 This is the same for all instructions except: Branch and Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel imm16 Instruction 0 1

CS 61C L34 Single Cycle CPU Control I (22) Garcia, Spring 2004 © UCB Peer Instruction Suppose we’re writing a MIPS interpreter in Verilog. Which sequence below is best organization for the interpreter? A. repeat loop that fetches instructions B. while loop that fetches instructions C. Decodes instructions using case statement D. Decodes instr. using chained if statements E. Executes each instruction F. Increments PC by 4 1: ACEF 2: ADEF 3: AECF 4: AEDF 5: BCEF 6: BDEF 7: BECF 8: BEDF 9: EF 0: FAE

CS 61C L34 Single Cycle CPU Control I (23) Garcia, Spring 2004 © UCB °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °Control is the hard part °MIPS makes that easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Summary: Single cycle datapath Control Datapath Memory Processor Input Output