9/13/05ELEC5970-001/6970-001 Lecture 61 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

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Presentation transcript:

9/13/05ELEC / Lecture 61 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Dynamic Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

9/13/05ELEC / Lecture 62 CMOS Dynamic Power Dynamic Power = Σ0.5 α i f clk C Li V DD 2 All gates i ≈ 0.5 α f clk C L V DD 2 ≈ α 01 f clk C L V DD 2 whereαaverage gate activity factor α 01 = 0.5α, average 0→1 trans. f clk clock frequency C L total load capacitance V DD supply voltage

9/13/05ELEC / Lecture 63 Example: 0.25μm CMOS Chip f = 500MHz Average capacitance = 15fF/gate V DD = 2.5V 10 6 gates Power= α 01 f C L V DD 2 = α 01 ×500×10 6 ×(15× ×10 6 ) ×2.5 2 = 46.9W, for α 01 = 1.0

9/13/05ELEC / Lecture 64 Signal Activity, α T=1/f Clock α 01 = 1.0 α 01 = 0.5 Comb. signals

9/13/05ELEC / Lecture 65 Reducing Dynamic Power Dynamic power reduction is –Quadratic with reduction of supply voltage –Linear with reduction of capacitance

9/13/05ELEC / Lecture μm CMOS Inverter, V DD =2.5V V in (V) V out (V) V in (V) Gain

9/13/05ELEC / Lecture μm CMOS Inverter, V DD < 2.5V V in (V) V out (V) V in (V) V out (V) Gain = -1

9/13/05ELEC / Lecture 68 Lower Bound on V DD For proper operation of gate, maximum gain (for Vin = V DD /2) should be greater than 1. Gain max = -(1/n)[exp(V DD /2Φ T ) – 1] = -1 n = 1.5 Φ T = kT/q = 26mV V DD = 48V V DDmin > 2 to 4 times kT/q or ~100mV at room temperature (27 o C) Ref.: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.

9/13/05ELEC / Lecture 69 Impact of V DD on Performance C L V DD Inverter delay = K─────── (V DD – V t ) α 0.6V1.8V3.0V V DD Power Delay Delay (ns) V DD =V t

9/13/05ELEC / Lecture 610 Optimum Power × Delay V DD 3 Power × Delay, PD=constant ×─────── (V DD – V t ) α For minimum power-delay product, d(PD)/dV DD = 0 3V t V DD =─── 3 – α For long channel devices, α = 2, V DD = 3V t For very short channel devices, α = 1, V DD = 1.5V t

9/13/05ELEC / Lecture 611 Transistor Sizing for Performance Problem: If we increase W/L to make the charging or discharging of load capacitance, then the increased W increases the load for the driving gate C in CLCL

9/13/05ELEC / Lecture 612 Fixed-Taper Buffer V in V out CLCL C in 1 α α2α2 α i-1 α n-1 C i = α i-1 C in C L = α n C in Delay = t 0 Ref.: J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, Piscataway, New Jersey: IEEE Press, 2004.

9/13/05ELEC / Lecture 613 Buffer (Cont.) α n = C L /C in ln (C L /C in ) n = ────── ln α ith stage delay, t i = αt 0, i = 1,... n, because each stage drives a stage α times bigger than itself.

9/13/05ELEC / Lecture 614 Buffer (Cont.) n Total delay =Σ ti=nαt 0 i=1 = ln(C L /C in ) αt 0 /ln(α)

9/13/05ELEC / Lecture 615 Buffer (Cont.) Differentiating total delay with respect to α and equating to 0, we get α opt = e ≈ 2.7 The optimum number of stages is n opt = ln(C L /C in )

9/13/05ELEC / Lecture 616 Further Reading B. S. Cherkauer and E. G. Friedman, “A Unified Design Methodology for CMOS Tapered Buffers,” IEEE Trans. VLSI Systems, vol. 3, no. 1, pp , March 1995.