Week 11Spring :332:331 Computer Architecture and Assembly Language Spring 2006 Week 11: Microprogramming [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]

Week 11Spring 2006 Simplifying Control Design  For an implementation of the full MIPS ISA l instructions can take from 1 clock cycle to 20 clock cycles l resulting in finite state machines with hundreds to thousands of states with even more arcs (state sequences)  Graphical representations become impossibly complex  Instead, represent the set of control signals that are asserted during a state as a low-level control “instruction” to be executed by the datapath microinstructions  “Executing” the microinstruction is equivalent to asserting the control signals specified by the microinstruction

Week 11Spring 2006 Microprogramming  Microinstruction has to specify l what control signals should be asserted l what microinstruction should be executed next  Each microinstruction corresponds to one state in the FSM and is assigned a state number (or “address”) 1. Sequential behavior – increment the state (address) of the current microinstruction to get to the state (address) of the next 2. Jump to the microinstruction that begins execution of the next MIPS instruction (state 0) 3. Branch to a microinstruction based on control unit input using dispatch tables -need one for microinstructions following state 1 -need another for microinstructions following state 2  The set of microinstructions that define a MPS assembly language instruction (macroinstruction) is its microroutine

Week 11Spring 2006 Defining a Microinstruction Format  Format – the fields of the microinstruction and the control signals that are affected by each field l control signals specified by a field usually have functions that are related l format is chosen to simplify the representation and to make it difficult to write inconsistent microinstructions -i.e., that allow a given control signal be set to two different values  Make each field of the microinstruction responsible for specifying a nonoverlapping set of control signals l signals that are never asserted simultaneously may share the same field l seven fields for our simple machine -ALU control; SRC1; SRC2; Register control; Memory; PCWrite control; Sequencing

Week 11Spring 2006 Review: Multicycle Data and Control Path Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control FSM IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

Week 11Spring 2006 Review: Multicycle RTL Summary StepR-typeMem RefBranchJump Instr fetch IR = Memory[PC]; PC = PC + 4; Decode A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC +(sign-extend(IR[15-0])<< 2); Execute ALUOut = A op B; ALUOut = A + sign-extend (IR[15-0]); if (A==B) PC = ALUOut; PC = PC[31-28] ||(IR[25-0] << 2); Memory access Reg[IR[15- 11]] = ALUOut; MDR = Memory[ALUOut]; or Memory[ALUOut] = B; Write- back Reg[IR[20-16]] = MDR;

Week 11Spring 2006 Our Microinstruction Format FieldValueSignal settingComments ALU control AddALUOp = 00Cause ALU to add SubtALUOp = 01Cause ALU to subtract (compare op for beq) Func codeALUOp = 10Use IR function code to determine ALU control SRC1PCALUSrcA = 0Use PC as top ALU input AALUSrcA = 1Use reg A as top ALU input SRC2BALUSrcB = 00Use reg B as bottom ALU input 4ALUSrcB = 01Use 4 as bottom ALU input ExtendALUSrcB = 10Use sign extension output as bottom ALU input ExtshftALUSrcB = 11Use shift-by-two output as bottom ALU input Register control ReadRead RegFile using rs and rt fields of IR as read addr’s; put data into A and B Write ALURegWrite, RegDst = 1, MemtoReg = 0 Write RegFile using rd field of IR as write addr and ALUOut as write data Write MDRRegWrite, RegDst = 0, MemtoReg = 1 Write RegFile using rt field of IR as write addr and MDR as write data

Week 11Spring 2006 Our Microinstruction Format, con’t FieldValueSignal settingComments MemoryRead PCMemRead, IorD = 0,IRWrite Read memory using PC as addr; write result into IR (and MDR) Read ALUMemRead, lorD = 1 Read memory using ALUOut as addr; write results into MDR Write ALUMemWrite, IorD = 1 Write memory using ALUOut as addr and B as write data PC write control ALUPCSource = 00 PCWrite Write PC with output of ALU ALUOut- cond PCSource = 01, PCWriteCond If Zero output of ALU is true, write PC with the contents of ALUOut Jump address PCSource = 10, PCWrite Write PC with IR jump address after shift-by- two Sequen- cing SeqAddrCtl = 11Choose next microinstruction sequentially FetchAddrCtl = 00Jump to the first microinstruction (i.e., Fetch) to begin a new instruction Dispatch 1AddrCtl = 01Branch using PLA_1 Dispatch 2AddrCtl = 10Branch using PLA_2

Week 11Spring 2006 Dispatch (Branch) Logic  Dispatch operations are implemented using special logic (PLAs) Microcode Dispatch PLA_1 Opcode field OpcodeValue (Addr) R-format Rexec (6) jmp Jump (9) beq Beq (8) lw Maddr (2) sw Maddr (2) Microcode Dispatch PLA_2 Opcode field OpcodeValue (Addr) lw Memlw (3) sw Memsw (5)

Week 11Spring 2006 Creating the Microprogram  Fetch microinstruction Label (Addr) ALU control SRC1SRC2Reg control MemoryPCWrite control Seq’ing Fetch (0) AddPC4Read PCALUSeq compute PC + 4 fetch instr into IR write ALU output into PC go to  instr 1  Label field represents the state (address) of the microinstruction  Fetch microinstruction assigned state (address) 0

Week 11Spring 2006 Creating the Microprogram, con’t  Decode microinstruction Label (Addr) ALU contro l SRC1SRC2Reg control MemoryPCWrit e control Seq’ing Decode (1)  Decode microinstruction assigned state (address) 1

Week 11Spring 2006 Creating the Microprogram, con’t  Decode microinstruction Label (Addr) ALU control SRC1SRC2Reg control MemoryPCWrite control Seq’ing Decode (1) AddPCExt shft ReadDisp 1 compute branch target (PC + sign_ext(IR[15- 0])<<2)) and store it in ALUOut use rs and rt to read RegFile and store output in A and B use dispatch table in ROM_1 to choose next  instr  Decode microinstruction assigned state (address) 1

Week 11Spring 2006 Creating the Microprogram, con’t  Memory-reference (lw & sw) microinstructions Label (Addr) ALU contro l SRC1SRC2Reg control MemoryPCWrit e control Seq’ing Maddr Memlw Memwb Memsw  Assigned states (addresses) 2, 3, 4, and 5

Week 11Spring 2006 Creating the Microprogram, con’t  Memory-reference (lw & sw) microinstructions Label (Addr) ALU control SRC1SRC2Reg controlMemoryPCWrite control Seq’ing Maddr (2) AddAExtendDisp 2 Memlw (3) Read ALUSeq Memwb (4) Write MDRFetch Memsw (5) Write ALUFetch compute memory address (RegFile(rs) + sign_ext(IR[15-0])) and store it in ALUOut on lw – first read memory at ALUOut and store output in MDR; then write MDR into RegFile at rt on sw – write B into memory at address in ALUOut  Assigned states (addresses) 2, 3, 4, and 5

Week 11Spring 2006 Creating the Microprogram, con’t  R-type instruction microinstructions Label (Addr) ALU contro l SRC1SRC2Reg control MemoryPCWrit e control Seq’ing Rexec Rwb  Assigned states (addresses) 6 and 7

Week 11Spring 2006 Creating the Microprogram, con’t  R-type instruction microinstructions Label (Addr) ALU control SRC1SRC2Reg control MemoryPCWrite control Seq’ing Rexec (6) Func code ABSeq Rwb (7) Write ALU Fetch perform the ALU operation specified in the instr. function field using contents of A and B and store the result in ALUOut when done, go to fetch cycle for next instruction  Assigned states (addresses) 6 and 7 write ALUOut in the RegFile at rd

Week 11Spring 2006 Creating the Microprogram, con’t  Branch (beq) and jump microinstructions Label (Addr) ALU control SRC1SRC2Reg control MemoryPCWrite control Seq’ing Beq Jump  Assigned states (addresses) 8 and 9

Week 11Spring 2006 Creating the Microprogram, con’t  Branch (beq) and jump microinstructions Label (Addr) ALU control SRC1SRC2Reg control MemoryPCWrite control Seq’ing Beq (8) SubtAB ALUOut- cond Fetch Jump (9) Jump address Fetch for beq – do operand comparison (A - B) to produce Zero output on j – load jump target addr into PC on beq – load ALUOut into PC if Zero is true  Assigned states (addresses) 8 and 9

Week 11Spring 2006 The Entire Control Microprogram AddrALU control SRC1SRC2Reg control MemoryPCWrite control Seq’ing 0AddPC4Read PCALUSeq 1AddPCExt shftReadDisp 1 2AddAExtendDisp 2 3Read ALUSeq 4 Write MDR Fetch 5 Write ALU Fetch 6 Func code ABSeq 7 Write ALU Fetch 8SubtAB ALUOut- cond Fetch 9Jump address Fetch

Week 11Spring 2006 Microprogram to Microcode  A microassember is used to convert the mnemonic microprogram into the actual control signals (0’s and 1’) or microcode, for example Label (Addr) ALU control SRC1SRC2Reg control MemoryPCWrite control Seq’ing Fetch (0) AddPC4Read PCALUSeq Label (Addr) ALU control SRC1SRC2Reg control MemoryPCWrite control Seq’ing ALUOpALU SrcA ALU SrcB RegWrite, RegDst, MemtoReg MemRead, MemWrite, IRWrite, IorD PCSource, PCWrite, PCWriteCond AddrCtl 00… ,X,X1,0,1,000, 1, X11

Week 11Spring 2006 Microcode Implementation Control PLA Inst[31-26] sequencing control Outputs Op0Op1Op2Op3Op4Op5 PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg PCSource ALUOp ALUSourceB ALUSourceA RegWrite RegDst System clock Microprogram Counter 1 Adder Addr select logic AddrCtl

Week 11Spring 2006 Address Select Logic Inst[31-26] Op0Op1Op2Op3Op4Op5 System ClockMicroprogram Counter AddrCtl (sequencing control from microcode memory) 1 Adder Addr select logic to control PLA Dispatch PLA_2 Dispatch PLA_1 0 dispatch table in PLA_2 to choose next  instr 3 or 5 dispatch table in PLA_1 to choose next  instr 2, 6, 8 or 9

Week 11Spring 2006 Review: FSM Implementation Combinational control logic State Reg Inst[31-26] Next State Inputs Outputs Op0Op1Op2Op3Op4Op5 PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg PCSource ALUOp ALUSourceB ALUSourceA RegWrite RegDst System Clock

Week 11Spring 2006 Control Path Design Alternatives Initial representation Sequencing control Logic representation Implementation technique Finite state diagram Microprogram Explicit next state function Microprogram counter + dispatch PLAs Microcode Logic equations Programmable Logic Array (PLA)  Microprogram representation advantages l Easier to design, write, and debug