CSE331 W11&12.1Irwin&Li Fall 2006 PSU CSE 331 Computer Organization and Design Fall 2006 Week 11&12 (Thanksgiving Week) Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)www.cse.psu.edu/~mji.

CSE331 W11&12.1Irwin&Li Fall 2006 PSU CSE 331 Computer Organization and Design Fall 2006 Week 11&12 (Thanksgiving Week) Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)www.cse.psu.edu/~mji Section 2: Feihui Li (www.cse.psu.edu/~feli )www.cse.psu.edu/~feli Course material on ANGEL: cms.psu.edu [ adapted from D. Patterson slides ]

CSE331 W11&12.2Irwin&Li Fall 2006 PSU Head’s Up  Last week’s material l Designing a MIPS single cycle datapath  This week’s material l Multicycle MIPS datapath implementation, microprogramming -Reading assignment – PH: 5.5, 5.7, B.10, C.3-C.5

CSE331 W11&12.3Irwin&Li Fall 2006 PSU Review: Single Cycle Data and Control Path Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Instr[31-26] Branch Shift left 2 0 1 Jump 28 Instr[25-0] 26 PC+4[31-28] 32

CSE331 W11&12.4Irwin&Li Fall 2006 PSU Single Cycle Disadvantages & Advantages  Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instr l especially problematic for more complex instructions like floating point multiply  May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but  It is simple and easy to understand Clk lwswWaste Cycle 1Cycle 2

CSE331 W11&12.5Irwin&Li Fall 2006 PSU Multicycle Implementation Overview  Each instruction step takes 1 clock cycle l Therefore, an instruction takes more than 1 clock cycle to complete  Not every instruction takes the same number of clock cycles to complete  Multicycle implementations allow l faster clock rates l different instructions to take a different number of clock cycles l functional units to be used more than once per instruction as long as they are used on different clock cycles, as a result -only need one memory -only need one ALU/adder

CSE331 W11&12.6Irwin&Li Fall 2006 PSU The Multicycle Datapath – A High Level View Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout  Registers have to be added after every major functional unit to hold the output value until it is used in a subsequent clock cycle

CSE331 W11&12.7Irwin&Li Fall 2006 PSU Clocking the Multicycle Datapath Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout System Clock MemWriteRegWrite clock cycle

CSE331 W11&12.8Irwin&Li Fall 2006 PSU  Break up the instructions into steps where each step takes a clock cycle while trying to l balance the amount of work to be done in each step l use only one major functional unit per clock cycle  At the end of a clock cycle l Store values needed in a later clock cycle by the current instruction in a state element (internal register not visible to the programmer) IR – Instruction Register MDR – Memory Data Register A and B – Register File read data registers ALUout – ALU output register -All (except IR) hold data only between a pair of adjacent clock cycles (so they don’t need a write control signal) l Data used by subsequent instructions are stored in programmer visible state elements (i.e., Register File, PC, or Memory) Multicycle Approach

CSE331 W11&12.9Irwin&Li Fall 2006 PSU The Complete Multicycle Data with Control Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.10Irwin&Li Fall 2006 PSU Review: Our ALU Control  Controlling the ALU uses of multiple decoding levels l main control unit generates the ALUOp bits l ALU control unit generates ALUcontrol bits Instr opfunctALUOpactionALUcontrol lwxxxxxx00add0110 swxxxxxx00add0110 beqxxxxxx01subtract1110 add10000010add0110 subt10001010subtract1110 and10010010and0000 or10010110or0001 xor10011010xor0010 nor10011110nor0011 slt10101010slt1111

CSE331 W11&12.11Irwin&Li Fall 2006 PSU  Reading/writing to l any of the internal registers or the PC occurs (quickly) at the end of a clock cycle l reading/writing to the Register File takes ~50% of a clock cycle since it has additional control and access overhead (reading can be done in parallel with decode)  Had to add multiplexors in front of several of the functional unit inputs because the functional unit input ports have multiple inputs since they are now shared by different clock cycles  All operations occurring in one clock cycle occur in parallel l This limits us to one ALU operation, one memory access, and one Register File access per clock cycle Multicycle Approach, con’t

CSE331 W11&12.12Irwin&Li Fall 2006 PSU 1. Instruction Fetch 2. Instruction Decode and Register Fetch 3. R-type Instruction Execution, Memory Read/Write Address Computation, Branch Completion, or Jump Completion 4. Memory Read Access, Memory Write Completion or R-type Instruction Completion 5. Memory Read Completion (Write Back) INSTRUCTIONS TAKE FROM 3 - 5 CYCLES! Five Instruction Steps

CSE331 W11&12.13Irwin&Li Fall 2006 PSU  Use PC to get instruction from the memory and put it in the Instruction Register  Increment the PC by 4 and put the result back in the PC  Can be described succinctly using the RTL "Register- Transfer Language“ IR = Memory[PC]; PC = PC + 4; Step 1: Instruction Fetch Can we figure out the values of the control signals? What is the advantage of updating the PC now?

CSE331 W11&12.14Irwin&Li Fall 2006 PSU Datapath Activity During Instruction Fetch Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.15Irwin&Li Fall 2006 PSU Datapath Activity During Instruction Fetch Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 00

CSE331 W11&12.16Irwin&Li Fall 2006 PSU Fetch Control Signals Settings Start Instr Fetch

CSE331 W11&12.17Irwin&Li Fall 2006 PSU Fetch Control Signals Settings Start Instr Fetch IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X

CSE331 W11&12.18Irwin&Li Fall 2006 PSU  Don’t know what the instruction is yet, so can only l Read registers rs and rt in case we need them l Compute the branch address in case the instruction is a branch  The RTL: A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC +(sign-extend(IR[15-0])<< 2);  Note we aren't setting any control lines based on the instruction (since we don’t know what it is (the control logic is busy "decoding" the op code bits)) Step 2: Instruction Decode and Register Fetch

CSE331 W11&12.19Irwin&Li Fall 2006 PSU Datapath Activity During Instruction Decode Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.20Irwin&Li Fall 2006 PSU Datapath Activity During Instruction Decode Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 00

CSE331 W11&12.21Irwin&Li Fall 2006 PSU Decode Control Signals Settings Start Instr Fetch Decode Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite

CSE331 W11&12.22Irwin&Li Fall 2006 PSU Decode Control Signals Settings Start Instr Fetch Decode ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X

CSE331 W11&12.23Irwin&Li Fall 2006 PSU  ALU is performing one of four functions, based on instruction type  Memory reference ( lw and sw ): ALUOut = A + sign-extend(IR[15-0]);  R-type: ALUOut = A op B;  Branch: if (A==B) PC = ALUOut;  Jump: PC = PC[31-28] || (IR[25-0] << 2); Step 3 (instruction dependent)

CSE331 W11&12.24Irwin&Li Fall 2006 PSU Datapath Activity During Instruction Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.25Irwin&Li Fall 2006 PSU Datapath Activity During lw & sw Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 00

CSE331 W11&12.26Irwin&Li Fall 2006 PSU Datapath Activity During R-type Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.27Irwin&Li Fall 2006 PSU Datapath Activity During R-type Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 10

CSE331 W11&12.28Irwin&Li Fall 2006 PSU Datapath Activity During R-type Completion Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.29Irwin&Li Fall 2006 PSU Datapath Activity During beq Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.30Irwin&Li Fall 2006 PSU Datapath Activity During beq Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 01

CSE331 W11&12.31Irwin&Li Fall 2006 PSU Datapath Activity During j Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.32Irwin&Li Fall 2006 PSU Datapath Activity During j Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.33Irwin&Li Fall 2006 PSU Execute Control Signals Settings Start Instr Fetch Decode Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite

CSE331 W11&12.34Irwin&Li Fall 2006 PSU Execute Control Signals Settings Start Instr Fetch Decode (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite Execute Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite

CSE331 W11&12.35Irwin&Li Fall 2006 PSU The x86 is an extremely complex instruction set architecture, and most of that complexity is embedded in the microcode.... Every time the microarchitecture must be changed, so must the microcode, and all fundamental changes to either will expose new areas in the microcode for which the past is a poor guide to correctness. The Pentium Chronicles, Colwell, pg. 66

CSE331 W11&12.36Irwin&Li Fall 2006 PSU  Memory reference: MDR = Memory[ALUOut]; -- lw or Memory[ALUOut] = B; -- sw  R-type instruction completion Reg[IR[15-11]] = ALUOut;  Remember, the register write actually takes place at the end of the cycle on the clock edge Step 4 (also instruction dependent)

CSE331 W11&12.37Irwin&Li Fall 2006 PSU Datapath Activity During Memory Access Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.38Irwin&Li Fall 2006 PSU Datapath Activity During lw Memory Access Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.39Irwin&Li Fall 2006 PSU Datapath Activity During sw Memory Access Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.40Irwin&Li Fall 2006 PSU Datapath Activity During R-type Completion Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.41Irwin&Li Fall 2006 PSU Memory Access Control Signals Settings Start Instr Fetch Decode Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite

CSE331 W11&12.42Irwin&Li Fall 2006 PSU Memory Access Control Signals Settings Start Instr Fetch Decode Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) MemRead IorD=1 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0 RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0 Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite

CSE331 W11&12.43Irwin&Li Fall 2006 PSU  All we have left is the write back into the register file the data just read from memory for lw instruction Reg[IR[20-16]]= MDR; What about all the other instructions? Step 5: Memory Read Completion (Write Back)

CSE331 W11&12.44Irwin&Li Fall 2006 PSU Datapath Activity During lw Write Back Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.45Irwin&Li Fall 2006 PSU Datapath Activity During lw Write Back Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE331 W11&12.46Irwin&Li Fall 2006 PSU Write Back Control Signals Settings Start Instr Fetch Decode Write Back Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0 MemRead IorD=1 PCWriteCond=0

CSE331 W11&12.47Irwin&Li Fall 2006 PSU Write Back Control Signals Settings Start Instr Fetch Decode Write Back Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) RegDst=0 RegWrite MemtoReg=1 PCWriteCond=0 Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite MemRead IorD=1 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0 RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0

CSE331 W11&12.48Irwin&Li Fall 2006 PSU RTL Summary StepR-typeMem RefBranchJump Instr fetch IR = Memory[PC]; PC = PC + 4; Decode A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC +(sign-extend(IR[15-0])<< 2); Execute ALUOut = A op B; ALUOut = A + sign-extend (IR[15-0]); if (A==B) PC = ALUOut; PC = PC[31-28] ||(IR[25- 0] << 2); Memory access Reg[IR[15 -11]] = ALUOut; MDR = Memory[ALUOut]; or Memory[ALUOut] = B; Write- back Reg[IR[20-16]] = MDR;

CSE331 W11&12.49Irwin&Li Fall 2006 PSU  How many cycles will it take to execute this code? lw $t2, 0($t3) lw $t3, 4($t3) beq $t2, $t3, Label #assume not add $t5, $t2, $t3 sw $t5, 8($t3) Label:...  What is going on during the 8 th cycle of execution?  In what cycle does the actual addition of $t2 and $t3 takes place?  In what cycle is the branch target address calculated? Answering Simple Questions

CSE331 W11&12.50Irwin&Li Fall 2006 PSU  How many cycles will it take to execute this code? lw $t2, 0($t3) lw $t3, 4($t3) beq $t2, $t3, Label #assume not add $t5, $t2, $t3 sw $t5, 8($t3) Label:...  What is going on during the 8 th cycle of execution?  In what cycle does the actual addition of $t2 and $t3 takes place?  In what cycle is the branch target address calculated? Answering Simple Questions 5 3 4 = 21 cycles address for second lw being calculated 16 th cycle 12 th cycle

CSE331 W11&12.51Irwin&Li Fall 2006 PSU  Multicycle datapath control signals are not determined solely by the bits in the instruction l e.g., op code bits tell what operation the ALU should be doing, but not what instruction cycle is to be done next  We can use a finite state machine for control l a set of states (current state stored in State Register) l next state function (determined by current state and the input) l output function (determined by current state)  So we are using a Moore machine (datapath control signals based only on current state) Multicycle Control Combinational control logic State Reg Inst Opcode Datapath control points Next State...

CSE331 W11&12.52Irwin&Li Fall 2006 PSU Multicycle Datapath Finite State Machine Start Instr Fetch Decode Write Back Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) 01 2 3 4 5 6 7 8 9 Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite MemRead IorD=1 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0 RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0 RegDst=0 RegWrite MemtoReg=1 PCWriteCond=0

CSE331 W11&12.53Irwin&Li Fall 2006 PSU Finite State Machine Implementation Combinational control logic State Reg Inst[31-26] Next State Inputs Outputs Op0Op1Op2Op3Op4Op5 PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg PCSource ALUOp ALUSourceB ALUSourceA RegWrite RegDst System Clock

CSE331 W11&12.54Irwin&Li Fall 2006 PSU Datapath Control Outputs Truth Table OutputsInput Values (Current State[3-0]) 0000000100100011010001010110011110001001 PCWrite1000000001 PCWriteCondX00000001X IorD0XX1X1XXXX MemRead1001000000 MemWrite0000010000 IRWrite1000000000 MemtoRegXXXX1XX0XX PCSource00XX 0110 ALUOp00 XX 10XX01XX ALUSrcB011110XX 00XX00XX ALUSrcA001XXX1X1X RegWrite0000100100 RegDstXXXX0XX1XX

CSE331 W11&12.55Irwin&Li Fall 2006 PSU Next State Truth Table Current State [3-0] Inst[31-26] (Op[5-0]) 000000 (R- type) 000010 (jmp) 000100 (beq) 100011 (lw) 101011 (sw) Any other 00000001 0110100110000010 illegal 0010XXXX 00110101illegal 0011XXXX 0100XXXXillegal 0100XXXX 0000XXXXillegal 0101XXXX 0000illegal 01100111XXXX illegal 01110000XXXX illegal 1000XXXX 0000XXXX illegal 1001XXXX0000XXXX illegal

CSE331 W11&12.56Irwin&Li Fall 2006 PSU Simplifying the Control Unit Design  For an implementation of the full MIPS ISA instr’s can take from 1 clock cycle to 20+ clock cycles l resulting in finite state machines with hundreds to thousands of states with even more arcs (state sequences) -Such state machine representations become impossibly complex  Instead, can represent the set of control signals that are asserted during a state as a low-level control “instruction” to be executed by the datapath microinstructions  “Executing” the microinstruction is equivalent to asserting the control signals specified by the microinstruction

CSE331 W11&12.57Irwin&Li Fall 2006 PSU Microprogramming  A microinstruction has to specify l what control signals should be asserted l what microinstruction should be executed next  Each microinstruction corresponds to one state in the FSM and is assigned a state number (or “address”) 1. Sequential behavior – increment the state (address) of the current microinstruction to get to the state (address) of the next 2. Jump to the microinstruction that begins execution of the next MIPS instruction (state 0) 3. Branch to a microinstruction based on control unit input using dispatch tables -need one for microinstructions following state 1 -need another for microinstructions following state 2  The set of microinstructions that define a MIPS assembly language instruction (macroinstruction) is its microroutine

CSE331 W11&12.58Irwin&Li Fall 2006 PSU Defining a Microinstruction Format  Format – the fields of the microinstruction and the control signals that are affected by each field l control signals specified by a field usually have functions that are related l format is chosen to simplify the representation and to make it difficult to write inconsistent microinstructions -i.e., that allow a given control signal be set to two different values  Make each field of the microinstruction responsible for specifying a nonoverlapping set of control signals l signals that are never asserted simultaneously may share the same field l seven fields for our simple machine -ALU control; SRC1; SRC2; Register control; Memory; PCWrite control; Sequencing

CSE331 W11&12.59Irwin&Li Fall 2006 PSU Our Microinstruction Format FieldValueSignal settingComments ALU control AddALUOp = 00Cause ALU to add SubtALUOp = 01Cause ALU to subtract (compare op for beq) Func codeALUOp = 10Use IR function code to determine ALU control SRC1PCALUSrcA = 0Use PC as top ALU input AALUSrcA = 1Use reg A as top ALU input SRC2BALUSrcB = 00Use reg B as bottom ALU input 4ALUSrcB = 01Use 4 as bottom ALU input ExtendALUSrcB = 10Use sign ext output as bottom ALU input ExtshftALUSrcB = 11Use shift-by-two output as bottom ALU input Register control ReadRead RegFile using rs and rt fields of IR as read addr’s; put data into A and B Write ALURegWrite, RegDst = 1, MemtoReg = 0 Write RegFile using rd field of IR as write addr and ALUOut as write data Write MDR RegWrite, RegDst = 0, MemtoReg = 1 Write RegFile using rt field of IR as write addr and MDR as write data

CSE331 W11&12.60Irwin&Li Fall 2006 PSU Our Microinstruction Format, con’t FieldValueSignal settingComments MemoryRead PCMemRead, IorD = 0,IRWrite Read memory using PC as addr; write result into IR (and MDR) Read ALUMemRead, lorD = 1 Read memory using ALUOut as addr; write results into MDR Write ALUMemWrite, IorD = 1 Write memory using ALUOut as addr and B as write data PC write control ALUPCSource = 00 PCWrite Write PC with output of ALU ALUOut- cond PCSource = 01, PCWriteCond If Zero output of ALU is true, write PC with the contents of ALUOut Jump address PCSource = 10, PCWrite Write PC with IR jump address after shift-by-two Sequen- cing SeqAddrCtl = 11Choose next microinstruction sequentially FetchAddrCtl = 00Jump to the first microinstruction (i.e., Fetch) to begin a new instruction Dispatch 1AddrCtl = 01Branch using PLA_1 Dispatch 2AddrCtl = 10Branch using PLA_2

CSE331 W11&12.61Irwin&Li Fall 2006 PSU Microprogram sequencer Defines what the next microinstruction will be

CSE331 W11&12.62Irwin&Li Fall 2006 PSU Dispatch (Branch) Logic  Dispatch operations are implemented using special logic (PLAs) Microcode Dispatch PLA_1 Opcod e field OpcodeValue (Addr) 000000R-format Rexec (6) 000010jmp Jump (9) 000100beq Beq (8) 100011lw Maddr (2) 101011sw Maddr (2) Microcode Dispatch PLA_2 Opcode field OpcodeValue (Addr) 100011lw Memlw (3) 101011sw Memsw (5)

CSE331 W11&12.63Irwin&Li Fall 2006 PSU Creating the Microprogram  Fetch microinstruction Label (Addr) ALU control SRC1SRC2Reg control MemoryPCWrite control Seq’ing Fetch (0) AddPC4Read PCALUSeq compute PC + 4fetch instr into IR write ALU output into PC go to  instr 1  Label field represents the state (address) of the microinstruction  Fetch microinstruction assigned state (address) 0

CSE331 W11&12.64Irwin&Li Fall 2006 PSU The Entire Control Microprogram AddrALU control SRC1SRC2Reg control MemoryPCWrite control Seq’ing 0AddPC4Read PCALUSeq 1AddPC Ext shft ReadDisp 1 2AddAExtendDisp 2 3Read ALUSeq 4 Write MDR Fetch 5 Write ALU Fetch 6 Func code ABSeq 7 Write ALU Fetch 8SubtAB ALUOut- cond Fetch 9Jump address Fetch

CSE331 W11&12.65Irwin&Li Fall 2006 PSU Microcode Implementation Control PLA Inst[31-26] sequencing control Outputs Op0Op1Op2Op3Op4Op5 PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg PCSource ALUOp ALUSourceB ALUSourceA RegWrite RegDst System clock Microprogram Counter 1 Adder Addr select logic AddrCtl

CSE331 W11&12.66Irwin&Li Fall 2006 PSU Control Path Design Alternatives Initial representation Sequencing control Logic representation Implementation technique Finite state diagram Microprogram Explicit next state function Microprogram counter + dispatch PLAs Microcode Logic equations Programmable Logic Array (PLA)  Microprogram representation advantages l Easier to design, write, and debug

CSE331 W11&12.67Irwin&Li Fall 2006 PSU Multicycle Advantages & Disadvantages  Uses the clock cycle efficiently – the clock cycle is timed to accommodate the slowest instruction step l balance the amount of work to be done in each step l restrict each step to use only one major functional unit  Multicycle implementations allow l faster clock rates l different instructions to take a different number of clock cycles l functional units to be used more than once per instruction as long as they are used on different clock cycles but  Requires additional internal state registers, muxes, and more complicated (FSM) control

CSE331 W11&12.68Irwin&Li Fall 2006 PSU Single Cycle vs. Multiple Cycle Timing Clk Cycle 1 Multiple Cycle Implementation: IFetchDecExecMemWB Cycle 2Cycle 3Cycle 4Cycle 5Cycle 6Cycle 7Cycle 8Cycle 9Cycle 10 IFetchDecExecMem lwsw IFetch R-type Clk Single Cycle Implementation: lwsw Waste Cycle 1Cycle 2 multicycle clock slower than 1/5 th of single cycle clock due to state register overhead

CSE331 W11&12.1Irwin&Li Fall 2006 PSU CSE 331 Computer Organization and Design Fall 2006 Week 11&12 (Thanksgiving Week) Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)www.cse.psu.edu/~mji.

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Presentation on theme: "CSE331 W11&12.1Irwin&Li Fall 2006 PSU CSE 331 Computer Organization and Design Fall 2006 Week 11&12 (Thanksgiving Week) Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)www.cse.psu.edu/~mji."— Presentation transcript:

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CSE331 W11&12.1Irwin&Li Fall 2006 PSU CSE 331 Computer Organization and Design Fall 2006 Week 11&12 (Thanksgiving Week) Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)www.cse.psu.edu/~mji.

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Presentation on theme: "CSE331 W11&12.1Irwin&Li Fall 2006 PSU CSE 331 Computer Organization and Design Fall 2006 Week 11&12 (Thanksgiving Week) Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)www.cse.psu.edu/~mji."— Presentation transcript:

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