Part 4 - Exception Hazards – one last kicker 3/24/04 Similar problem as the conditional branch An exception is an involuntary branch from a non-branching instruction that caused the exception Example: add $1, $2, $1 # assume the add overflows –We need to immediately branch to the exception handler at entry point address: 0x –Must flush the instructions following the “add” & start fetching from the new address in the exception handler. –Overflow is detected in the EX stage – this is where the “add” will be Must kill the “add” instruction dead in its tracks and not allow it to complete - so it will not clobber $1 – a valuable diagnostic for the programmer. –Do not allow this instruction to write results in WB stage. –Contrast this to the conditional jump, in which the beq instruction (that caused the jump) was allowed to complete.

Exception Hazards: Data Path Changes Insert a nop in the IF stage –Must be done directly – no control signals in IF/ID register –Need new control line, IF.Flush, from main controller Flush instruction in ID stage –Zero out control signals –Need new control line, ID.Flush, from main controller ORed with the stall signal from Hazard Detection Unit for beq Flush instruction in EX stage – the add instruction itself –Zero out control signals –Need new control line, EX.Flush, from main controller –beq did not flush this stage Add additional input to PC MUX providing 0x jump address to the exception handler. Save PC+4 in EPC register – exception handler will have to subtract 4 to get the address of the offending instruction.

Data Path with Exception Hazard Support Fig The selector for the PC MUX must now be 2 bits: a line indicating the exception and the compare output – Not mentioned in book?

An Example Scenario Given the main program: 0x40 sub $11, $2, $4 0x44 and $12, $2, $5 0x48 or $13, $2, $6 0x4C add $1, $2, $1 # overflow happens here 0x50 slt $15, $6, $7 0x54 lw $16, 50($7) Assume the exception handler starts with: 0x sw $25, 1000($0) 0x sw $26, 1004($0) See fig 6.56 for response of data path. –Overflow detected during EX phase –0x forced into PC –Cycle 6 shows the add and following instructions are flushed First instruction of exception handler is fetched address following add is saved in EPC: 0x4C+4 = 0x50

Data Paths for Exception Scenario Fig 6.56