1. The Processor Lecture 3.6: Control Hazards
Be aware that this first part of new chapter 4 is review for this class, so doesn’t go into detail. If your students are learning computer organization for the first time, this set of slides needs to be expanded greatly.

2. Learning Objectives
Move branch decision hardware into the decode stage
Resolve data hazards for branch instruction

3. Coverage
Chapter 4.8

4. MIPS Pipeline Control Path Modifications1
The width of each pipeline registers.
IF/ID: 32+32=64 bits
ID/EX:32*4+5*2+9=147 bits
EX/MEM: 32* =107 bits
MEM/WB: 32*2+5+2=71 bits.

5. Control Hazards
When the flow of instruction addresses is not sequential (i.e., PC ≠ PC + 4); incurred by change of flow instructions
Unconditional branches (j, jal, jr)
Conditional branches (beq, bne)
Exceptions
Possible approaches
Stall (impacts CPI)
Move decision point as early in the pipeline as possible, thereby reducing the number of stall cycles
Predict and hope for the best!
Delay decision (requires compiler support)
Control hazards occur less frequently than data hazards, but there is nothing as effective against control hazards as forwarding is for data hazards

6. Branch Instr’s Cause Control Hazards
Dependencies backward in time cause hazards
beq
ALU IM
Reg DM I n s t r. O r d e
ALU IM
Reg DM lw
ALU IM
Reg DM
Inst 3
ALU IM
Reg DM
Inst 4

7. One Way to “Fix” a Branch Control Hazard
Fix branch hazard by waiting – flush – but affects CPI
ALU IM
Reg DM
beq I n s t r. O r d e
ALU IM
Reg DM
flush
ALU IM
Reg DM
flush
ALU IM
Reg DM
flush
beq target
ALU IM
Reg DM
Inst

8. Another Way to “Fix” a Branch Control Hazard
Move branch decision hardware as early in the pipeline as possible, i.e., during the decode cycle
ALU IM
Reg DM
beq I n s t r. O r d e
ALU IM
Reg DM
flush
beq target
ALU IM
Reg DM
Inst
Another “solution” is to put in enough extra hardware so that we can test registers, calculate the branch address, and update the PC during the second stage of the pipeline. That would reduce the number of stalls to only one.

9. Reducing the Delay of Branches
Add hardware to compute the branch target address and evaluate the branch decision to the ID stage
Reduces the number of stall (flush) cycles to one (like with jumps)
But now need to add forwarding hardware in ID stage
Comparing and updating the PC adds 2 muxes, a comparator, and an and gate to the ID stage
Computing branch target address can be done in parallel with RegFile read (done for all instructions – only used when needed)
Comparing the registers can be done in the same clock cycle as RegFile read
For deeper pipelines, branch decision points can be even later in the pipeline, incurring more stalls
Want a small branch penalty.
Need more forwarding and hazard detection hardware for second option (one stall implementation) since a branch depended on a result still in the pipeline (that is one of the source operands for the comparison logic) must be forwarded from the EX/MEM or MEM/WB pipeline latches.

10. Supporting ID Stage Branches
PCSrc
Branch
Hazard
Unit
ID/EX
IF.Flush 1
EX/MEM
IF/ID
Control
Add
MEM/WB 4
Shift
left 2
Add
Compare
Read Addr 1
Instruction
Memory
Data
Memory
RegFile
Read Addr 2
Read
Address PC
Read Data 1
Read Data
Write Addr
ALU
Address
ReadData 2
Write Data
Write Data
ALU
cntrl
Now IF.Flush is generated by the Hazard Unit for both jumps and for taken branches.
Book claims that you have to forward from the MEM/WB pipeline latch, but with RegFile write before read, I don’t think that is the case!! No need to forward from MEM/WB pipeline register.
IF.Flush will change the value of the IF/ID to zero to flush the instruction
The write signals to PC, IF/ID, and the multiplexor to change the value before the ID/EX pipeline register is to stall the Branch instruction itself. 16
Sign
Extend 32
Forward
Unit
Forward
Unit

11. Example: Branch Taken
Example
36: sub $10, $4, $8 40: beq $1, $3, 7 44: and $12, $2, $5 48: or $13, $2, $6 52: add $14, $4, $2 56: slt $15, $6, $
68: add $1, $2, $3 72: lw $4, 50($7)
76: and $3, $1, $2

12. Example: Branch Taken

13. Example: Branch Taken
72 should be is latched into the pipeline register.

14. Data Hazards for Branches
If a comparison register is a destination of 2nd preceding ALU instruction
Can resolve using forwarding IF ID EX
MEM WB
add $1, $2, $3 IF ID EX
MEM WB
add $4, $5, $6 IF ID EX
MEM WB
Inst 3
Which is forwarding, which is not forwarding?
$4 is forwarding, $1 does not need forwarding. IF ID EX
MEM WB
beq $1, $4, target

15. Data Hazards for Branches
If a comparison register is a destination of preceding ALU instruction or 2nd preceding load instruction
Need 1 stall cycle IF ID EX
MEM WB
lw $1, addr IF ID EX
MEM WB
add $4, $5, $6
beq stalled IF ID
Again, $4 needs forwarding, $1 does not need forwarding
beq $1, $4, target ID EX
MEM WB

16. Data Hazards for Branches
If a comparison register is a destination of immediately preceding load instruction
Need 2 stall cycles
But no data forwarding IF ID EX
MEM WB
lw $1, addr
beq stalled IF ID
beq stalled ID
No forwarding is needed.
beq $1, $0, target ID EX
MEM WB