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The processor: Pipelining and Branching

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1 The processor: Pipelining and Branching
Morgan Kaufmann Publishers 17 November, 2018 CSF 2009 The processor: Pipelining and Branching Chapter 4 Chapter 4 — The Processor 1

2 Morgan Kaufmann Publishers
17 November, 2018 Branch Hazards If branch outcome determined in MEM Flush these instructions (Set control values to 0) PC Chapter 4 — The Processor — 2 Chapter 4 — The Processor

3 Morgan Kaufmann Publishers
17 November, 2018 Reducing Branch Delay Move hardware to determine outcome to ID stage Target address adder Register comparator Example: branch taken 36: sub $10, $4, $8 40: beq $1, $3, 7 44: and $12, $2, $5 48: or $13, $2, $6 52: add $14, $4, $2 56: slt $15, $6, $ : lw $4, 50($7) Chapter 4 — The Processor — 3 Chapter 4 — The Processor

4 Morgan Kaufmann Publishers
17 November, 2018 Example: Branch Taken Chapter 4 — The Processor — 4 Chapter 4 — The Processor

5 Morgan Kaufmann Publishers
17 November, 2018 Example: Branch Taken Chapter 4 — The Processor — 5 Chapter 4 — The Processor

6 Data Hazards for Branches
Morgan Kaufmann Publishers 17 November, 2018 Data Hazards for Branches If a comparison register is a destination of 2nd or 3rd preceding ALU instruction IF ID EX MEM WB add $1, $2, $3 IF ID EX MEM WB add $4, $5, $6 IF ID EX MEM WB … IF ID EX MEM WB beq $1, $4, target Can resolve using forwarding Chapter 4 — The Processor — 6 Chapter 4 — The Processor

7 Data Hazards for Branches
Morgan Kaufmann Publishers 17 November, 2018 Data Hazards for Branches If a comparison register is a destination of preceding ALU instruction or 2nd preceding load instruction Need 1 stall cycle IF ID EX MEM WB lw $1, addr IF ID EX MEM WB add $4, $5, $6 beq stalled IF ID beq $1, $4, target ID EX MEM WB Chapter 4 — The Processor — 7 Chapter 4 — The Processor

8 Data Hazards for Branches
Morgan Kaufmann Publishers 17 November, 2018 Data Hazards for Branches If a comparison register is a destination of immediately preceding load instruction Need 2 stall cycles IF ID EX MEM WB lw $1, addr beq stalled IF ID beq stalled ID beq $1, $0, target ID EX MEM WB Chapter 4 — The Processor — 8 Chapter 4 — The Processor

9 Dynamic Branch Prediction
Morgan Kaufmann Publishers 17 November, 2018 Dynamic Branch Prediction In deeper and superscalar pipelines, branch penalty is more significant Use dynamic prediction Branch prediction buffer (aka branch history table) Indexed by recent branch instruction addresses Stores outcome (taken/not taken) To execute a branch Check table, expect the same outcome Start fetching from fall-through or target If wrong, flush pipeline and flip prediction Chapter 4 — The Processor — 9 Chapter 4 — The Processor

10 1-Bit Predictor: Shortcoming
Morgan Kaufmann Publishers 17 November, 2018 1-Bit Predictor: Shortcoming Inner loop branches mispredicted twice! outer: … … inner: … … beq …, …, inner … beq …, …, outer Mispredict as taken on last iteration of inner loop Then mispredict as not taken on first iteration of inner loop next time around Chapter 4 — The Processor — 10 Chapter 4 — The Processor

11 Morgan Kaufmann Publishers
17 November, 2018 2-Bit Predictor Only change prediction on two successive mispredictions Chapter 4 — The Processor — 11 Chapter 4 — The Processor

12 Calculating the Branch Target
Morgan Kaufmann Publishers 17 November, 2018 Calculating the Branch Target Even with predictor, still need to calculate the target address 1-cycle penalty for a taken branch Branch target buffer Cache of target addresses Indexed by PC when instruction fetched If hit and instruction is branch predicted taken, can fetch target immediately Chapter 4 — The Processor — 12 Chapter 4 — The Processor

13 The processor: Exceptions and Interrupts
Morgan Kaufmann Publishers 17 November, 2018 CSF 2009 The processor: Exceptions and Interrupts Chapter 4 Chapter 4 — The Processor 13

14 Exceptions and Interrupts
Morgan Kaufmann Publishers 17 November, 2018 Exceptions and Interrupts “Unexpected” events requiring change in flow of control Different ISAs use the terms differently Exception Arises within the CPU e.g., undefined opcode, overflow, syscall, … Interrupt From an external I/O controller Dealing with them without sacrificing performance is hard Chapter 4 — The Processor — 14 Chapter 4 — The Processor

15 Morgan Kaufmann Publishers
17 November, 2018 Handling Exceptions In MIPS, exceptions managed by a System Control Coprocessor (CP0) Save PC of offending (or interrupted) instruction In MIPS: Exception Program Counter (EPC) Save indication of the problem In MIPS: Cause register We’ll assume 1-bit 0 for undefined opcode, 1 for overflow Jump to handler at Chapter 4 — The Processor — 15 Chapter 4 — The Processor

16 An Alternate Mechanism
Morgan Kaufmann Publishers 17 November, 2018 An Alternate Mechanism Vectored Interrupts Handler address determined by the cause Example: Undefined opcode: C Overflow: C …: C Instructions either Deal with the interrupt, or Jump to real handler Chapter 4 — The Processor — 16 Chapter 4 — The Processor

17 Morgan Kaufmann Publishers
17 November, 2018 Handler Actions Read cause, and transfer to relevant handler Determine action required If restartable Take corrective action use EPC to return to program Otherwise Terminate program Report error using EPC, cause, … Chapter 4 — The Processor — 17 Chapter 4 — The Processor

18 Exceptions in a Pipeline
Morgan Kaufmann Publishers 17 November, 2018 Exceptions in a Pipeline Another form of control hazard Consider overflow on add in EX stage add $1, $2, $1 Prevent $1 from being clobbered Complete previous instructions Flush add and subsequent instructions Set Cause and EPC register values Transfer control to handler Similar to mispredicted branch Use much of the same hardware Chapter 4 — The Processor — 18 Chapter 4 — The Processor

19 Pipeline with Exceptions
Morgan Kaufmann Publishers 17 November, 2018 Pipeline with Exceptions Chapter 4 — The Processor — 19 Chapter 4 — The Processor

20 Morgan Kaufmann Publishers
17 November, 2018 Exception Properties Restartable exceptions Pipeline can flush the instruction Handler executes, then returns to the instruction Refetched and executed from scratch PC saved in EPC register Identifies causing instruction Actually PC + 4 is saved Handler must adjust Chapter 4 — The Processor — 20 Chapter 4 — The Processor

21 Morgan Kaufmann Publishers
17 November, 2018 Exception Example Exception on add in 40 sub $11, $2, $4 44 and $12, $2, $5 48 or $13, $2, $6 4C add $1, $2, $1 50 slt $15, $6, $7 54 lw $16, 50($7) … Handler sw $25, 1000($0) sw $26, 1004($0) … Chapter 4 — The Processor — 21 Chapter 4 — The Processor

22 Morgan Kaufmann Publishers
17 November, 2018 Exception Example Chapter 4 — The Processor — 22 Chapter 4 — The Processor

23 Morgan Kaufmann Publishers
17 November, 2018 Exception Example Chapter 4 — The Processor — 23 Chapter 4 — The Processor

24 Morgan Kaufmann Publishers
17 November, 2018 Multiple Exceptions Pipelining overlaps multiple instructions Could have multiple exceptions at once Simple approach: deal with exception from earliest instruction Flush subsequent instructions “Precise” exceptions In complex pipelines Multiple instructions issued per cycle Out-of-order completion Maintaining precise exceptions is difficult! Chapter 4 — The Processor — 24 Chapter 4 — The Processor

25 Morgan Kaufmann Publishers
17 November, 2018 Imprecise Exceptions Just stop pipeline and save state Including exception cause(s) Let the handler work out Which instruction(s) had exceptions Which to complete or flush May require “manual” completion Simplifies hardware, but more complex handler software Not feasible for complex multiple-issue out-of-order pipelines Chapter 4 — The Processor — 25 Chapter 4 — The Processor

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