SIDECAR ASIC Control Electronics on a Chip June 24 th 2005 Markus Loose

ML, Detector Workshop, June 2005 Chart 2 Replace this with this! 1% volume 1% power 1% hassle The SIDECAR ASIC Control Electronics on a Chip

ML, Detector Workshop, June 2005 Chart 3 SIDECAR Architecture Digital Control Microcontroller for Clock Generation and Signal Processing Bias Generator Amplification and A/D Conversion Data Memory Program Memory Data Memory Digital I/O Interface SIDECAR External Electronics Multiplexer, e.g. HAWAII-2RG analog mux out bias voltages clocks main clock data in data out synchron. Digital Generic I/O SIDECAR: S ystem for I mage D igitization, E nhancement, C ontrol and R etrieval

ML, Detector Workshop, June 2005 Chart 4 SIDECAR Feature List 36 analog input channels, each channel provides: – 500 kHz A/D conversion with 16 bit resolution – 10 MHz A/D conversion with 12 bit resolution – gain = 0 dB …. 27 dB in steps of 3 dB – optional low-pass filter with programmable cutoff – optional internal current source (as source follower load) 16 bit low-power microprocessor core (single event upset proof) – responsible for timing generation and data processing – 16 kwords program memory (32 kByte) and 8 kwords data memory (16 kByte) – 36 kwords ADC data memory, 24 bit per word (108 kByte) – additional array processor for adding, shifting and multiplying on all 36 data channels in parallel (e.g. on-chip CDS, leaky memory or other data processing tasks) 32 digital I/O channels to generate clock patterns, each channel provides: – input / output / highohmic – selectable output driver strength and polarity – pattern generator (16 bit pattern) independent of microcontroller – programmable delay (1ns - 250µs) 20 analog output channels, each channel provides: – programmable output voltage and driver strength – programmable current source or current sink – internal reference generation (bandgap or vdd)

ML, Detector Workshop, June 2005 Chart 5 Microcontroller Block Diagram

ML, Detector Workshop, June 2005 Chart 6 Sample Micro Code Subsection of the assembler code for reading a complete frame of the H2RG Shows the innermost loop that reads one row of pixels pixelloop: BCLR R6,10 // set data storage address BCLR R7,10 // to lower memory block // ADC 7 SUB R3,h60 ST (R3),R5 // enable ADC test bus driver IN R0,Strobe OUT STROBEREG,R0 // set ADC conversion trigger IN R0,TestHigh // read upper 2 ADC bits MOVLH RX0,R0 IN R0,TestLow // read lower 16 ADC bits MOVW RX0,R0 SHR RX0,2 // reduce ADC data to 16 bits MOVW R0,RX0 ST (R6),R0 // store ADC data in memory ST (R3),R4 // disable ADC test bus driver // ADC 15 ADD R3,h20 ST (R3),R5 // enable ADC test bus driver IN R0,ADCDefault OUT STROBEREG,R0 // reset ADC trigger IN R0,TestHigh // read upper 2 ADC bits MOVLH RX0,R0 IN R0,TestLow // read lower 16 ADC bits MOVW RX0,R0 SHR RX0,2 // reduce ADC data to 16 bits OUT LowerClks,R1 // HCLK => 0 MOVW R0,RX0 ST (R7),R0 // store ADC data in memory ST (R3),R4 // disable ADC test bus driver pixelloop: BCLR R6,10 // set data storage address BCLR R7,10 // to lower memory block // ADC 7 SUB R3,h60 ST (R3),R5 // enable ADC test bus driver IN R0,Strobe OUT STROBEREG,R0 // set ADC conversion trigger IN R0,TestHigh // read upper 2 ADC bits MOVLH RX0,R0 IN R0,TestLow // read lower 16 ADC bits MOVW RX0,R0 SHR RX0,2 // reduce ADC data to 16 bits MOVW R0,RX0 ST (R6),R0 // store ADC data in memory ST (R3),R4 // disable ADC test bus driver // ADC 15 ADD R3,h20 ST (R3),R5 // enable ADC test bus driver IN R0,ADCDefault OUT STROBEREG,R0 // reset ADC trigger IN R0,TestHigh // read upper 2 ADC bits MOVLH RX0,R0 IN R0,TestLow // read lower 16 ADC bits MOVW RX0,R0 SHR RX0,2 // reduce ADC data to 16 bits OUT LowerClks,R1 // HCLK => 0 MOVW R0,RX0 ST (R7),R0 // store ADC data in memory ST (R3),R4 // disable ADC test bus driver BSET R6,10 // set data storage address BSET R7,10 // to upper memory block // ADC 23 ADD R3,h20 ST (R3),R5 // enable ADC test bus driver IN R0,TestHigh // read upper 2 ADC bits MOVLH RX0,R0 IN R0,TestLow // read lower 16 ADC bits MOVW RX0,R0 SHR RX0,2 // reduce ADC data to 16 bits MOVW R0,RX0 ST (R6),R0 // store ADC data in memory ST (R3),R4 // disable ADC test bus driver // ADC 31 ADD R3,h20 ST (R3),R5 // enable ADC test bus driver IN R0,TestHigh // read upper 2 ADC bits MOVLH RX0,R0 IN R0,TestLow // read lower 16 ADC bits MOVW RX0,R0 SHR RX0,2 // reduce ADC data to 16 bits MOVW R0,RX0 ST (R7),R0 // store ADC data in memory ST (R3),R4 // disable ADC test bus driver OUT LowerClks,R2 // HCLK => 1 INC R6 // increment address for ADC7/23 DEC RX3 // decrement pixel counter JPNZ pixelloop,DLY,LKY // jump if RX3 not zero DEC R7 // decrement address for ADC15/31 BSET R6,10 // set data storage address BSET R7,10 // to upper memory block // ADC 23 ADD R3,h20 ST (R3),R5 // enable ADC test bus driver IN R0,TestHigh // read upper 2 ADC bits MOVLH RX0,R0 IN R0,TestLow // read lower 16 ADC bits MOVW RX0,R0 SHR RX0,2 // reduce ADC data to 16 bits MOVW R0,RX0 ST (R6),R0 // store ADC data in memory ST (R3),R4 // disable ADC test bus driver // ADC 31 ADD R3,h20 ST (R3),R5 // enable ADC test bus driver IN R0,TestHigh // read upper 2 ADC bits MOVLH RX0,R0 IN R0,TestLow // read lower 16 ADC bits MOVW RX0,R0 SHR RX0,2 // reduce ADC data to 16 bits MOVW R0,RX0 ST (R7),R0 // store ADC data in memory ST (R3),R4 // disable ADC test bus driver OUT LowerClks,R2 // HCLK => 1 INC R6 // increment address for ADC7/23 DEC RX3 // decrement pixel counter JPNZ pixelloop,DLY,LKY // jump if RX3 not zero DEC R7 // decrement address for ADC15/31

ML, Detector Workshop, June 2005 Chart 7 ASIC Floorplan

ML, Detector Workshop, June 2005 Chart 8 SIDECAR Micrograph 22 mm 14.5 mm

ML, Detector Workshop, June 2005 Chart 9 Callouts of Various Layout Sections Inside the ASIC PreAmp 16-bit ADC Instr. Memory Micro-Controller Logo

ML, Detector Workshop, June 2005 Chart 10 Test Results – Warm and Cryogenic The SIDECAR ASIC has been tested at room temperature and cryogenically. Cryogenic tests have been carried out at 37K (JWST) The correct operation of all blocks has been verified: – Microcontroller – Memories (except dual port memory due to leakage problem) – Digital I/O block (clock generation) – Bias generation – Data interface to external electronics – 12-bit ADC – 16-bit ADC – PreAmp All blocks operate consistently and show the same or improved performance at cryogenic temperatures compared to room temperature.

ML, Detector Workshop, June 2005 Chart bit ADC Results Measured at 7.5 MHz Sample Rate Output Code DNL [ LSB ] DNL Output Code INL [ LSB ] INL Differential Non-Linearity: < ± 0.3 LSB Integral Non-Linearity: < ± 0.7 LSB Temporal Noise at 300 K < 0.4 LSB

ML, Detector Workshop, June 2005 Chart bit ADC Results Measured at 125 kHz Sample Rate Output Code DNL [ LSB ] DNL Output Code INL [ LSB ] INL Differential Non-Linearity: < ± 0.3 LSB Integral Non-Linearity: < ± 0.2 LSB Temporal Noise at 300 K < 5 LSB Temporal Noise at 77 K < 3 LSB

ML, Detector Workshop, June 2005 Chart 13 SIDECAR Driving HAWAII-2RG PC IDL Software for SIDECAR Control and Data Capture PCI Card with FPGA & Memory Vreset Dsub Clock 000 w 384 w 0cd w HAWAII-2RG SIDECAR ASIC Analog Supply Data In Data Out Master Clock Digital Supply 3.3V Analog Video Biases Power Supply Serial Interface Clocks Only 7 lines needed to operate the SIDECAR ASIC in base configuration (3 signal & 4 power lines) The SIDECAR ASIC provides all 27 signals required to operate the HAWAII-2RG The microcontroller driven SIDECAR ASIC generates all biases & clocks and digitizes the analog video outputs Sensor Chip Assembly Inside the dewar at T = 37K

ML, Detector Workshop, June 2005 Chart 14 HAWAII-2RG with 2.5 µm cutoff HgCdTe CDS of two consecutive frames CDS noise: 16 e- Better than conventional controller Noise Results – Differential Operation

ML, Detector Workshop, June 2005 Chart 15 Total CDS Noise in 1000s Method 1: Difference of two CDS frames divided by. The CDS noise is given by the width of the distribution. noise = 16.3 e- Method 2: Take many CDS frames and look at each pixel’s variation from frame to frame. The CDS noise is given by the mean of the distribution. noise = 15.6 e-

ML, Detector Workshop, June 2005 Chart 16 Total Fowler 8-8 Noise in 1000s Method 1: Difference of two Fowler 8- 8 ramps divided by. The noise is given by the width of the distribution. noise = 6.7 e- Method 2: Take many Fowler 8-8 ramps and look at each pixel’s variation from ramp to ramp. The noise is given by the mean of the distribution. noise = 6.8 e- Meets NIRCam noise of 9e-

ML, Detector Workshop, June 2005 Chart 17 Total Up-The-Ramp Noise (1000s) Method 1: Difference of two ramps (22 x 4 frames each) divided by. The noise is given by the width of the distribution. noise = 4.95 e- Method 2: Take many ramps and look at the slope variation from ramp to ramp for each pixel. The noise is given by the mean of the distribution. noise = 5.2 e- Meets NIRSpec noise of 6e-

ML, Detector Workshop, June 2005 Chart 18 Noise Reduces With Fowler n-n Two ramps, 146 frames each, have been analyzed with respect to noise reduction by Fowler sampling for a 1000s integration time. With Fowler 64-64, the read noise is reduced to 3.6 e- Theoretical noise reduction assuming same initial CDS noise Actual noise reduction when using measured SIDECAR data

ML, Detector Workshop, June 2005 Chart 19 The ASIC has demonstrated excellent noise performance that exceeds the requirements for all three near-infrared instruments ASIC Exceeds JWST Noise Requirements LeachSIDECAR CDS (Fowler 1-1) 16.9 e- (72 µV) 15.4 e- (65.6 µV) Fowler e- (29.7 µV) 6.4 e- (27.3 µV) Noise at low bias Noise at medium bias Noise, 200 kHz sampling JWST Requirement ASIC by itself (NIRSpec 4-22 multiaccum) 2.0 e-1.8 e-1.4 e- 2.4 e - (NIRSpec) ASIC + HAWAII-2RG CDS 16.5 e-16.2 e-12.5 e- 24 e- (extrapolated) ASIC + HAWAII-2RG Fowler e-6.7 e-5.1 e- 9 e- (NIRCAM) ASIC + HAWAII-2RG (4 –22 multiaccum) 5.3 e-5.2 e-*4 e- 6 e- (NIRSpec) Direct comparison with discrete electronics (Leach controller) shows superior ASIC performance: * Multiaccum calculated using only 4 out of 6 measured ramps to reduce frame-to-frame pedestal.

ML, Detector Workshop, June 2005 Chart 20 ASIC Flight Package for JWST Focal Plane Array SIDECAR ASIC Exploded View Detector + ASIC Sub-System

ML, Detector Workshop, June 2005 Chart 21 Conclusion Full functionality has been demonstrated Noise performance is comparable to or exceeds performance of conventional controllers Significantly smaller and lower power than discrete electronics: – Can be placed inside the dewar  fully digital camera system – The solution for large mosaics Operates from room temperature down to 30 K ASIC has been selected by JWST as the detector controller for NIRCAM, NIRSpec and FGS. ASICs for ground-based astronomy will be available within ~3 months – Cryogenically suitable 337-pin LGA package – USB-based interface electronics for easy hook-up to a PC – Complete suite of software tools (Assembler, Integrated design&test environment) First ASIC version showed significant leakage current in the dual-port memory – Problem has been fixed in second ASIC revision – Rev2 ASICs have just arrived at Rockwell Scientific and are currently being tested – First results indicate that the leakage problem has been completely resolved