8/30/05ELEC5970-001/6970-001 Lecture 31 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

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8/30/05ELEC / Lecture 31 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Capacitance in a CMOS Circuit Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

8/30/05ELEC / Lecture 32 Capacitances In Out C1C1 C2C2 V DD GND CWCW

8/30/05ELEC / Lecture 33 Miller Capacitance In Out C1C1 C2C2 V DD GND CWCW CMCM

8/30/05ELEC / Lecture 34 Before Transition In Out C1C1 C2C2 V DD GND CWCW CMCM 0 +V DD

8/30/05ELEC / Lecture 35 After Transition In Out C1C1 C2C2 V DD GND CWCW CMCM 0 -V DD Energy from supply = 2 C M V DD 2 Effective capacitance = 2 C M

8/30/05ELEC / Lecture 36 Capacitances in MOSFET SourceDrain Gate oxide Gate Bulk CsCs CdCd CgCg C gd C gs

8/30/05ELEC / Lecture 37 Bulk nMOSFET n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon

8/30/05ELEC / Lecture 38 Gate Capacitance C g = C ox WL = C 0, intrinsic cap. C g = C permicron W ε ox C permicron =C ox L=── L t ox where ε ox = 3.9ε 0 for Silicon dioxide = 3.9×8.85× F/cm

8/30/05ELEC / Lecture 39 Intrinsic Capacitances Capacitance Region of operation CutoffLinearSaturation CgbC0C0 00 Cgs0C 0 /22/3 C 0 Cgd0C 0 /20 Cg = Cgs+Cgd+Cgb C0C0 C0C0 2/3 C 0 Weste and Harris, CMOS VLSI Design, Addison-Wesley, 2005, p. 78.

8/30/05ELEC / Lecture 310 Low-Power Transistors Device scaling to reduce capacitance and voltage. Body bias to reduce threshold voltage and leakage. Multiple threshold CMOS (MTCMOS). Silicon on insulator (SOI)

8/30/05ELEC / Lecture 311 Device Scaling Reduced dimensions –Reduce supply voltage –Reduce capacitances –Reduce delay –Increase leakage due to reduced V DD / V t

8/30/05ELEC / Lecture 312 Optimum Threshold Voltage V DD / V t Delay or Energy-delay product Delay Energy-delay product V t = 0.7V V t = 0.3V

8/30/05ELEC / Lecture 313 Bulk CMOS Inverter Polysilicon (input) SiO 2 p+ n+ p+ n+ n-well p-substrate (bulk) metal 1 VDDGND Output