ADC Performance Metrics, Measurement and Calibration Techniques Tibi Galambos Jan 2009

Outline Performance metrics of ADC Definitions (INL, DNL, ENOB, SNDR) Measurement techniques - histogram method A glimpse at ADC state of the art Calibration techniques for ADC (overview) stating the problem classification of techniques examples

ADC Performance metrics – A High Level ADC Model The signal to noise and distortion ratio (SNDR) (assuming a full scale single tone input) is: Based on the SNDR, the effective number of bits ENOB are defined as:

ADC Performance metrics – Static Characteristic of an Ideal ADC Decision levels: Quantization error (noise): Assumes uniform signal PDF over the code bin. ADC Resolution: For a full-scale single tone signal quantized by an ideal ADC: ENOB definition

ADC Performance metrics – Offset and Gain Error Offset and gain errors can be defined by end-to-end or by best fit. End-to end definitions (using the outer decision levels):

ADC Performance metrics – INL and DNL INL (integral non-linearity) and DNL (differential non-linearity) are defined AFTER correcting for linear (offset and gain) errors. INL can be interpreted as the distance between the actual decision level and the decision level of an ideal ADC that has been gain and offset corrected expressed in VLSB units. The DNL expresses the difference between the actual and the ideal code bin widths in VLSB units. The first and last code bin widths are defined by extension by VLSB, so that by definition:

ADC Performance metrics – From INL to ENOB There is no simple conversion from the two metrics, however: The mean square error (quantization and distortion) can be calculated (assuming the input signal has an uniform probability density function): (uniform PDF input) We observe that equation above contains the quantization and the distortion components. Making the further assumption that are uncorrelated, with a normal distribution of standard deviation then we get: (uniform PDF input) For signals that do not have an uniform probability density function, assuming the probability density is uniform within each code bin we get: where is the probability that the input signal is within code bin i.

ADC Performance – A Glimpse at ADC State of the Art (1) ADC performance is limited by fundamental laws of nature R.H. Walden, “Analog-to-digital converter survey and analysis,” IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, pp. 539-550, April 1999.

ADC Performance – A Glimpse at ADC State of the Art (2) Additional performance metrics are customary: Progress in ADC performance in terms of ENOB is slow R.H. Walden, “Analog-to-digital converter survey and analysis,” IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, pp. 539-550, April 1999.

ADC Performance – A Glimpse at ADC State of the Art (3) Progress in ADC power consumption (Figure of Merit) is fast Yun Chiu; Gray, P.R.; Nikolic, B.,"A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR", IEEE Journal of Solid-State Circuits, , Volume: 39 , Issue: 12 , Dec. 2004

ADC Performance – A Glimpse at ADC State of the Art (4) Where do we stand today? Research papers quote net power, industrial data is for a packaged ADC

ADC Performance – A Glimpse at ADC State of the Art (4) Recent trends in ADC design Very high sampling rate modest resolution low power converters for serial communications High complexity DSP-intensive solutions ADC power has decreased x10 in the last decade, In the same period, digital circuit power has decreased x100. SNR > 50 digital is very cheap SNR >70 it is for free. New design paradigm: analog, DSP and system level have to go hand in hand.

ADC Measurement Techniques – The Histogram Method Setup for ADC Characterization For measurement purposes we need a very accurate signal source - single and dual tone sources are used In order to get a clean measurement, a very large number of samples is required A convenient way to reduce the storage requirements for the samples is to collect a histogram: count the occurrences h(i) of each code bin I The normalized cumulative normalized histogram is defined: The spectral purity of the signal applied to the ADC is very important The jitter on the clock source has to be well controlled The clock and signal frequencies have to be close to independent to make sure all possible clock-signal phase relationships are swept

ADC Measurement Techniques – The Histogram Method Sine Wave Quantization If we know the signal amplitude and offset we can calculate the decision levels from the normalized cumulative histogram of the code bins The signal at the input of the ADC is usually not directly accessible for measurement: The parameters A and d have to be estimated Note: V is measured here in LSB units

ADC Measurement Techniques – The Histogram Method Simple Sine Fitting The simplest way to estimate the parameters A and d is to assume the outmost excited decision levels are correct If l and h are respectively the lowest and highest non-empty code bins, we assume Vl+1 and Vh-1 to be correct. (Reminder- V is in LSB units) Next All the decision levels can be estimated and then the INL and DNL The ENOB and SNDR parameters can also be estimate from the histogram data For accurate results a more sophisticated sine fitting method has to be used that uses the whole of the information in the histogram.

ADC Calibration Techniques – Definition of the Problem ADC calibration techniques aim to improve the overall performance of a given ADC by means of added circuitry

Limitations of ADC Calibration Techniques Calibration techniques can not cancel: Random effects (thermal noise, jitter) Quantization noise (an 8 bit ADC can not become 9 bit after calibration) Fast events (spikes, metastability)

Classification of ADC Calibration Techniques (1) By the domain of the correction: Analog calibration techniques Adjust reference voltages Adjust components (capacitors, resistors) Dynamic matching techniques Digital calibration techniques No adjustment is performed on the analog circuitry Some analog calibration source is always needed (By the nature of the problem any calibration technique is a mixed-mode circuit)

By the time the correction is performed: Classification of ADC Calibration Techniques (2) By the time the correction is performed: Background calibration techniques Calibration circuits run in parallel and not interfering with the normal functioning of the ADC Off-line calibration techniques Require a specially allocated training mode Offline calibration can be performed At fabrication (expensive, done at testing time) At power-up Periodically (but it incurs inactive times)

Classification of ADC Calibration Techniques (3) By the nature of the underlying ADC model : Static calibration The ADC is described by a static (memory-less) non-linear function Dynamic (slope dependent) impairments can not be corrected Dynamic calibration The ADC is described by a non-linear dynamic system Increased complexity of the calibration technique

Analog Calibration by Capacitor Trimming (in pipe-line ADC) The Capacitor Trimming Technique by Capacitor Divider Network Comparator Based Trimming Technique Delta-Sigma Trimming Technique Limitations and Benefits of Trimming

Capacitor Divider (1) In practice several taps are built and the trimming is done with a resolution of up to 3-4 bits

Capacitor Divider (2) Parasitic capacitances on the floating nodes increase the effect of parasitic capacitances to the substrate Depending on technology, non-discharged floating nodes can be a problem The additional switches used for trimming will increase the leakage problems

Comparator Based Trimming Technique The comparator can use the stage amplifier Offset Cancellation is needed This is an off-line technique At the end of phase F2: Y.-M. Lin, B. Kim, and P. R. Gray, “A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-um CMOS,” IEEE J. Solid-State Circuits, vol. 26, pp. 628–636, Apr. 1991

Delta-Sigma Based Trimming Technique Calibration only when The error term in this case has a constant sign This is an fully background technique Seung-Tak Ryu, Sourja Ray, Bang-Sup Song, Gyu-Hyeong Cho, and Kanti Bacrania ,"A 14-b Linear Capacitor Self-Trimming Pipelined ADC", IEEE Journal of Solid-State Circuits, VOL. 39, NO. 11, November 2004

Benefits & Limitations of Trimming If we implement a 3 bit trimming we can gain ~ 2 bits over the matching given by the capacitors The price of trimming is paid in Complexity Power Increased sensitivity to parasitic capacitance / leakage Trimming should be used only for the first stages of the pipe-line ADC to get closer to the thermal limited capacitor size

This is an off-line digital static calibration technique Digital Calibration by the Precision Bootstrapping Algorithm (in pipe-line ADC) (1) This is an off-line digital static calibration technique The analog calibration source is a DC voltage - advantage The control machine for the training sequence is complicated E. G. Soenen and R. L. Geiger, “An architecture and an algorithm for fully digital correction of monolithic pipelined ADC’s,” IEEE Trans. Circuits Syst. II, vol. 42, pp. 143–153, Mar. 1995.

Effect and Limitations of Fully Digital Calibration Digital Calibration by the Precision Bootstrapping Algorithm (in pipe-line ADC) (2) Effect and Limitations of Fully Digital Calibration The output of the ADC is a higher resolution representation but the decision points are the same as for an un-calibrated ADC. INL is improved but DNL not and even non-monotone errors can occur.

Digital Calibration with State Space Error Table This is an off-line digital dynamic calibration technique The analog calibration source is a known-statistics signal source Theoretically higher order dynamic calibrations are possible J . Tsimbinos K,.V. Lever “Improved error-table compensation of A/D converters” IEE Proc.-Circuits Devices Syst., Vol. 144, No 6, December 1997

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