Download presentation

Presentation is loading. Please wait.

Published byMay Waters Modified over 6 years ago

1
Fischer 08 1 Analog to Digital Converters Nyquist-Rate ADCs Flash ADCs Sub-Ranging ADCs Folding ADCs Pipelined ADCs Successive Approximation (Algorithmic) ADCs Integrating (serial) ADCs Oversampling ADCs Delta-Sigma based ADCs

2
Fischer 08 2 Conversion Principles

3
Fischer 08 3 ADC Architectures Flash ADCs: High speed, but large area and high power dissipation. Suitable for low-medium resolution (6-10 bit). Sub-Ranging ADCs: Require exponentially fewer comparators than Flash ADCs. Hence, they consume less silicon area and less power. Pipelined ADCs: Medium-high resolution with good speed. The trade- offs are latency and power. Successive Approximation ADCs: Moderate speed with medium- high resolution (8-14 bit). Compact implementation. Integrating ADCs or Ramp ADCs: Low speed but high resolution. Simple circuitry. Delta-Sigma based ADCs: Moderate bandwidth due to oversampling, but very high resolution thanks to oversampling and noise shaping.

4
Fischer 08 4 Performance Limitations 1 Thermal Noise LimitationClock Jitter (Aperture) Limitation Normalized Noise Powers: Limiting Condition: n-Bit ADC Sinusoidal Input Swing: ±1[V] f max = ½ f conv System Definitions Maximum Resolution: f in =½f conv

5
Fischer 08 5 Performance Limitations 2 Selection of ADC Architecture is driven by Application Displays Audio Sonar Ultra Sound Video Wireless Communications Seismology

6
Fischer 08 6 Parallel or Flash ADCs Conceptual Circuit

7
Fischer 08 7 Sub-Ranging ADCs Half-Flash or Two-Step ADC

8
Fischer 08 8 Folding ADCs Principle Configuration … 2 n1 Sub-Ranges

9
Fischer 08 9 Folding Processor Example: 2-Bit Folding Circuit ( 2 n-1 +1)Io for n-Bit 2Io

10
Fischer 08 10 Successive Approx. ADCs Concept Implementation

11
Fischer 08 11 DAC Realization 1 (Voltage Mode)

12
Fischer 08 12 DAC Realization 2 Spread Reduction through R-2R Ladder

13
Fischer 08 13 DAC Realization 3 Charge-Redistribution Circuit Pros Insensitive w.r.t. Op-amp Gain Offset (1/f Noise) compensated Cons Requires non-overlapping Clock High Element Spread Area Output requires S&H valid only during 2

14
Fischer 08 14 DAC Realization 4 Spread Reduction through capacitive Voltage Division valid only during 2 Spread=2 n/2 Example: 8-Bit ADC

15
Fischer 08 15 DAC Realization 5 Charge-Redistribution Circuit with Unity-Gain Amplifier Pros Voltage divider reduces spread Buffer low output impedance No clock required Cons Parasitic cap causes gain error High Op-amp common mode input required No amplifier offset compensation Amplifier Input Cap. Cp Gain Error: є G =-Cp/16C 16/15C Spread=½2 n/2 Example: 8-Bit ADC

16
Fischer 08 16 DAC8 with Unity-Gain Amplifier Sub-range Output (4 LSBs) 00.5u2u1.5u2.5u3.5u4.5u5.5u6.5u3u4u5u6u1u Amplifier Output 6.5u00.5u2u1.5u2.5u3.5u4.5u5.5u3u4u5u6u1u

17
Fischer 08 17 DAC Realization 6 Current Mode Implementation

18
Fischer 08 18 Current Cell & Floor Plan Unit Current Cell Symmetrical Current Cell Placement Current summing RailIout Cascode Current Source Switching Devices Array of 256 Cells R

19
Fischer 08 19 DAC Implementation Layout of 10-Bit Current-Mode DAC ( 0.5 m CMOS) Current summing Rails

20
Fischer 08 20 Modified SA Algorithm 1 Idea: Replace DAC by an Accumulator Consecutively divide Ref by 2

21
Fischer 08 21 Modified SA Algorithm 2 First cycle only Accumulator Idea: Maintain Comparator Reference (½ FS=Gnd) Double previous Accumulator Output

22
Fischer 08 22 SC Implementation SC Implementation of modified SA ADC

23
Fischer 08 23 Timing Diagram

24
Fischer 08 24 Offset Compensated Circuit Offset Compensated SC Implementation

25
Fischer 08 25 Building Blocks 1 DC Gain77 dB Gain- bandwidth 104 MHz @ CL= 1.5 pF Power 1.3 mW Output Swing 4 V p-p Transconductance Amplifier

26
Fischer 08 26 Building Blocks 2 Power 0.5 mW Resolution > 0.5 mV Settling Time 3 ns Latched CMOS Comparator

27
Fischer 08 27 Layout of 8-Bit ADC 165 m (0.5 m CMOS)

28
Fischer 08 28 Spice Simulation (Bsim3) 8-Bit ADC: fclk=10MHz fconv=1.25MHz

29
Fischer 08 29 Pipelined ADCs Pipelined modified SA or Algorithmic ADC Pros Offset (1/f Noise) compensated Minimum C-spread One conversion every clock period Cons Matching errors digital correction for n>8 Clock feed-through very critical High amplifier slew rate required

30
Fischer 08 30 Integrating or Serial ADCs Dual Slope ADC Concept Constant Ramp Prop. to Input Ramp Using 2 N /k samples requires Ref = FS/k reduced Integrator Constant (Element Spread) N represents digital equivalent of analog Input

31
Fischer 08 31 SC Dual-Slope ADC 10-Bit Dual-Slope ADC

32
Fischer 08 32 ADC Testing Types of Tests Static Testing Dynamic Testing In static testing, the input varies slowly to reveal the actual code transitions. Yields INL, DNL, Gain and Offset Error. Dynamic testing shows the response of the circuit to rapidly changing signals. This reveals settling errors and other dynamic effects such as inter-modulation products, clock-feed-trough, etc. Circuit Under Test Output Input Clock

33
Fischer 08 33 Performance Metrics 1 Error Types Offset Gain DNL INL Missing Codes IDEAL ADC Static Errors

34
Fischer 08 34 Performance Metrics 2 Frequency Domain Characterization Ideal n-Bit ADC: SNR = 6.02 x n + 1.76 [dB] fsig Amplitude

35
Fischer 08 35 ADC Error Sources Static Errors Element or Ratio Mismatches Finite Op-amp Gain Op-amp & Comparator Offsets Deviations of Reference Dynamic Errors Finite (Amplifier) Bandwidth Op-amp & Comparator Slew Rate Clock Feed-through Noise (Resistors, Op-amps, switched Capacitors) Intermodulation Products (Signal and Clock)

36
Fischer 08 36 Static Testing Servo-loop Technique Comparator, integrator, and ADC under test are in negative feedback loop to determine the analog signal level required for every digital code transition. Integrator output represents equivalent analog value of digital output. Transition values are used to generate input/output characteristic of ADC, which reveals static errors like Offset, Gain, DNL and INL.

37
Fischer 08 37 Dynamic Testing Types of Dynamic Tests Histogram or Code-Density Test FFT Test Sine Fitting Test Test Set-up

38
Fischer 08 38 Histogram or Code-Density Test DNL appears as deviation of bin height from ideal value. Integral nonlinearity (INL) is cumulative sum (integral) of DNL. Offset is manifested by a horizontal shift of curve. Gain error shows as horizontal compression or decompression of curve.

39
Fischer 08 39 Histogram Test Pros and Cons of Histogram Test Histogram test provides information on each code transition. DNL errors may be concealed due to random noise in circuit. Input frequency must be selected carefully to avoid missing codes (f clk /f in must be non-integer ratio). Input Swing is critical (cover full range) Requires a large number of conversions (o 2 n x 1,000).

40
Fischer 08 40 Simulated Histogram Test 8-Bit SA ADC with 0.5% Ratio Error and 5mV/V Comparator Offset

41
Fischer 08 41 FFT Test Pros and Cons of FFT Test Offers quantitative Information on output Noise, Signal- to-Noise Ratio (SNR), Spurious Free Dynamic Range (SFDR) and Harmonic Distortion (SNDR). FFT test requires fewer conversions than histogram test. Complete characterization requires multiple tests with various input frequencies. Does not reveal actual code conversions

42
Fischer 08 42 Simulated FFT Test 8-Bit SA ADC with 0.5% Ratio Error and 5mV/V Comparator Offset SFDR=60 dB SNDR=49 dB ENOB=7.85

Similar presentations

© 2021 SlidePlayer.com Inc.

All rights reserved.

To make this website work, we log user data and share it with processors. To use this website, you must agree to our Privacy Policy, including cookie policy.

Ads by Google