Fischer 08 3 ADC Architectures Flash ADCs: High speed, but large area and high power dissipation. Suitable for low-medium resolution (6-10 bit). Sub-Ranging ADCs: Require exponentially fewer comparators than Flash ADCs. Hence, they consume less silicon area and less power. Pipelined ADCs: Medium-high resolution with good speed. The trade- offs are latency and power. Successive Approximation ADCs: Moderate speed with medium- high resolution (8-14 bit). Compact implementation. Integrating ADCs or Ramp ADCs: Low speed but high resolution. Simple circuitry. Delta-Sigma based ADCs: Moderate bandwidth due to oversampling, but very high resolution thanks to oversampling and noise shaping.
Fischer 08 4 Performance Limitations 1 Thermal Noise LimitationClock Jitter (Aperture) Limitation Normalized Noise Powers: Limiting Condition: n-Bit ADC Sinusoidal Input Swing: ±1[V] f max = ½ f conv System Definitions Maximum Resolution: f in =½f conv
Fischer 08 5 Performance Limitations 2 Selection of ADC Architecture is driven by Application Displays Audio Sonar Ultra Sound Video Wireless Communications Seismology
Fischer 08 6 Parallel or Flash ADCs Conceptual Circuit
Fischer 08 7 Sub-Ranging ADCs Half-Flash or Two-Step ADC
Fischer 08 29 Pipelined ADCs Pipelined modified SA or Algorithmic ADC Pros Offset (1/f Noise) compensated Minimum C-spread One conversion every clock period Cons Matching errors digital correction for n>8 Clock feed-through very critical High amplifier slew rate required
Fischer 08 30 Integrating or Serial ADCs Dual Slope ADC Concept Constant Ramp Prop. to Input Ramp Using 2 N /k samples requires Ref = FS/k reduced Integrator Constant (Element Spread) N represents digital equivalent of analog Input
Fischer 08 32 ADC Testing Types of Tests Static Testing Dynamic Testing In static testing, the input varies slowly to reveal the actual code transitions. Yields INL, DNL, Gain and Offset Error. Dynamic testing shows the response of the circuit to rapidly changing signals. This reveals settling errors and other dynamic effects such as inter-modulation products, clock-feed-trough, etc. Circuit Under Test Output Input Clock
Fischer 08 34 Performance Metrics 2 Frequency Domain Characterization Ideal n-Bit ADC: SNR = 6.02 x n + 1.76 [dB] fsig Amplitude
Fischer 08 35 ADC Error Sources Static Errors Element or Ratio Mismatches Finite Op-amp Gain Op-amp & Comparator Offsets Deviations of Reference Dynamic Errors Finite (Amplifier) Bandwidth Op-amp & Comparator Slew Rate Clock Feed-through Noise (Resistors, Op-amps, switched Capacitors) Intermodulation Products (Signal and Clock)
Fischer 08 36 Static Testing Servo-loop Technique Comparator, integrator, and ADC under test are in negative feedback loop to determine the analog signal level required for every digital code transition. Integrator output represents equivalent analog value of digital output. Transition values are used to generate input/output characteristic of ADC, which reveals static errors like Offset, Gain, DNL and INL.
Fischer 08 37 Dynamic Testing Types of Dynamic Tests Histogram or Code-Density Test FFT Test Sine Fitting Test Test Set-up
Fischer 08 38 Histogram or Code-Density Test DNL appears as deviation of bin height from ideal value. Integral nonlinearity (INL) is cumulative sum (integral) of DNL. Offset is manifested by a horizontal shift of curve. Gain error shows as horizontal compression or decompression of curve.
Fischer 08 39 Histogram Test Pros and Cons of Histogram Test Histogram test provides information on each code transition. DNL errors may be concealed due to random noise in circuit. Input frequency must be selected carefully to avoid missing codes (f clk /f in must be non-integer ratio). Input Swing is critical (cover full range) Requires a large number of conversions (o 2 n x 1,000).
Fischer 08 40 Simulated Histogram Test 8-Bit SA ADC with 0.5% Ratio Error and 5mV/V Comparator Offset
Fischer 08 41 FFT Test Pros and Cons of FFT Test Offers quantitative Information on output Noise, Signal- to-Noise Ratio (SNR), Spurious Free Dynamic Range (SFDR) and Harmonic Distortion (SNDR). FFT test requires fewer conversions than histogram test. Complete characterization requires multiple tests with various input frequencies. Does not reveal actual code conversions
Fischer 08 42 Simulated FFT Test 8-Bit SA ADC with 0.5% Ratio Error and 5mV/V Comparator Offset SFDR=60 dB SNDR=49 dB ENOB=7.85