1. Converter common specs

2. Resolution
How fine the analog range is divided into finite number of discrete values
May be expressed in several different ways:
the weight of the Least Significant Bit (LSB)
parts per million of full-scale (ppm FS)
millivolts (mV), etc.
Different devices (even from the same manufacturer) will be specified differently
must translate between the different types of specifications if they are to compare devices successfully.

3. Quantization: The Size of a Least Significant Bit
10 bits with 1 V FS give 1mV, or 1000ppm, or 0.1% LSB

4. Ideal transfer curve of high resolution DAC/ADC place digital code with x, and analog value with y

5. 2’s compliment
11…11
10..00
01..11
00…00
-FS
0 V FS

6. GAIN AND OFFSET ERRORS

7. Offset and Gain error
Gain error FS
0 V
-FS

8. INTEGRAL NONLINEARITY ERRORS
INL measures how far away the actual transfer curve is from a linear fit line
INL_k is the amount of deviation at code k
INL is the maximum of INL_k
The fit line can be an end point to end point fit line
Or it could be best linear regression fit line

9. INTEGRAL NONLINEARITY ERRORS
input
voltage
code
code
Output code
Output code

10. differential nonlinearity
differential nonlinearity (DNL) relates how uniform the DAC output or ADC transition voltages are.
ideally, a change of 1 LSB in digital code corresponds to a change of exactly 1 LSB of analog voltage.
In a DAC, a change of 1 LSB in digital code produces exactly 1 LSB change of analog output,
In an ADC there should be exactly 1 LSB change of analog input to move from one transition to the next.
DNL_k is the amount of deviation of the analog interval away from 1 LSB when digital code transitions from k-1 to k
DNL is the maximum of all DNL_k

11. DAC Differential Nonlinearity

12. ADC Differential Nonlinearity

13. Missing code and nonmonotonicity

14. Transition uncertainty
Due to noise, jitter, aperture uncertain, the ADC’s transition points may seem to be uncertain.
It effects measurements of DNL

15. Example: 4 bit converter, Vref = 16 V
Code 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2^4 = 16 codes:
For DAC, these are input
For ADC, these are output
Unipolar converter.
Ideal analog step, or LSB is
Vref/2^N = 16V/2^4 = 1 V

16. For a DAC The ideal output would be: A total of 16 Vout = 1 2 3 4 5 61 2 3 4 5 6 7 8 9 10 11 12 13 14 15
The ideal output would be:
A total of 16

17. For an ADC The ideal transition voltages would be: A total of 15
Vtrans =
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
13.5
14.5
A total of 15

18. DAC actual output voltages:
Code 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Vout
Vos = Vout(0000) – IdealVout(0000)
= – 0
= V
= LSB
Gain error = {[Vout(1111)-Vout(0000)] – [Vref – 1 LSB]}/{ideal LSB}
= { – – 15}/{1}
= – LSB

19. If those are ADC transition voltages:
Code
0  1
1  2
2  3
3  4
4  5
5  6
6  7
7  8
8  9
9  10
10  11
11  12
12  13
13  14
14  15
Vtran
Vtrans index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Vos = Vtran(1) – IdealVtran(1)
= – 0.5
= V
= {1.0473V}/{ideal LSB} LSBs
Gain error = {[Vtran(2^N -1)-Vtran(1)] – [Vref – 2 LSB]}/{ideal LSB}
= { – – 14}/{1}
= – LSB

20. DAC actual LSB, step size
Code 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Vout
Vstep
1.6430
1.0661
0.4940
0.5091
0.6605
1.4770
0.6560
1.4400
0.6400
1.6010
0.7900
0.5760
0.6510
1.1630
0.9620
Actual LSB = average step
= V

21. ADC actual LSB, step size
index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Vtran
bin width
1.6430
1.0661
0.4940
0.5091
0.6605
1.4770
0.6560
1.4400
0.6400
1.6010
0.7900
0.5760
0.6510
1.1630
Actual LSB = average bin width
= V

22. DAC step size errors Code 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Vout1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Vout
Vstep
1.6430
1.0661
0.4940
0.5091
0.6605
1.4770
0.6560
1.4400
0.6400
1.6010
0.7900
0.5760
0.6510
1.1630
0.9620
linear
step
0.9552
Step
error
0.6878
0.1109
0.5218
0.4848
0.6458
0.2078
0.0068

23. DAC DNLk and INLk DNL= INL= Vos= VosLSB GELSB Code 1 2 3 4 5 6 7 8 91 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Vout
Vstep
1.6430
1.0661
0.4940
0.5091
0.6605
1.4770
0.6560
1.4400
0.6400
1.6010
0.7900
0.5760
0.6510
1.1630
0.9620
Estep
0.6878
0.1109
0.5218
0.4848
0.6458
0.2078
0.0068
DNLk
0.7200
0.1160
0.5462
0.5075
0.6760
0.2175
0.0071
INLk
0.7200
0.8360
0.3532
0.1238
0.3180
0.6639
0.4910
0.0939
DNL=
INL=
Vos=
VosLSB
GELSB
LSB = average step =

24. Finish the ADC example by yourself

25. How to obtain those voltages
For DAC:
Use a slow clock
Sequentially increase input code
At each code, use an accurate meter to measure Vout multiple times and average
For ADC:
Use an accurate signal generator
Select average hits per code, Havg
Set input step = LSB/Havg
Gradually increase input, one step at each clock
Count # hits for each code k, Hk
Bin width  hits,  use Hk in bin width column