ENEE350 Spring07 1 Ankur Srivastava University of Maryland, College Park Adapted from Computer Organization and Design, Patterson & Hennessy, © 2005.” Acknowledgement: Based on Slides By Mary Jane Irwin PSU Computer Systems Organization: Lecture 1

ENEE350 Spring07 2 Where is the Market? Millions of Computers

ENEE350 Spring07 3 Processor Performance Increase SUN-4/260MIPS M/120 MIPS M2000 IBM RS6000 HP 9000/750 DEC AXP/500 IBM POWER 100 DEC Alpha 4/266 DEC Alpha 5/500 DEC Alpha 21264/600 DEC Alpha 5/300 DEC Alpha 21264A/667 Intel Xeon/2000 Intel Pentium 4/3000

ENEE350 Spring07 4 DRAM Capacity Growth 16K 64K 256 K 1M 4M 16 M 64 M 128 M 256 M 512 M

ENEE350 Spring07 5 Impacts of Advancing Technology Processor –logic capacity:increases about 30% per year –performance:2x every 1.5 years Memory –DRAM capacity:4x every 3 years, now 2x every 2 years –memory speed:1.5x every 10 years –cost per bit:decreases about 25% per year Disk –capacity:increases about 60% per year

ENEE350 Spring07 6 Example Machine Organization CPU Computer Control Datapath MemoryDevices Input Output

ENEE350 Spring07 7 Giving instructions to a Computer We ordinarily program in a high level language like C, Java, would like to use human speech etc. Computers being digital machines understand the language of 0 and 1. How do we translate from a high level language to machine language How do computers take these instructions given in machine language and execute them.

ENEE350 Spring07 8 Giving instructions to a Computer Compiler High level Language Assembler Assembly Code Machine Code

ENEE350 Spring07 9 Giving instructions to a Computer Computer understand the language of 0 and 1 but we as programmers cannot code in them Around 70 S, assemblers were invented to translate so called assemply code into machine code. Assembly level code was a human readable instruction sequence for the computer. We will be disucssing the MIPS assembly code

ENEE350 Spring07 10 (vonNeumann) Processor Organization Control needs to 1.input instructions from Memory 2.issue signals to control the information flow between the Datapath components and to control what operations they perform 3.control instruction sequencing Fetch DecodeExec CPU Control Datapath MemoryDevices Input Output Datapath needs to have the –components – the functional units and storage (e.g., register file) needed to execute instructions –interconnects - components connected so that the instructions can be accomplished and so that data can be loaded from and stored to Memory

ENEE350 Spring07 11 Basic Datapath Organization Registers are a bank of flip flops. Are expensive to have in large numbers, therefore need to be augmented by memory (DRAMS, SRAMS, DISKS) ALURegistersMemory

ENEE350 Spring07 12 MIPS R3000 Instruction Set Architecture (ISA) Instruction Categories –Computational –Load/Store –Jump and Branch –Floating Point coprocessor –Memory Management –Special R0 - R31 PC HI LO Registers OP rs rt rdsafunct rs rt immediate jump target 3 Instruction Formats: all 32 bits wide R format I format J format

ENEE350 Spring07 13 Example of MIPS Instruction Add $t0, $s1, $s2 Sub $t0, $s1, $s2 destination  source1 op source2 The operands and the final destination are MIPS Registers