1. CPEN 315 - Digital System Design Chapter 10 – Instruction SET Architecture (ISA) © Logic and Computer Design Fundamentals, 4 rd Ed., Mano Prentice Hall © Computer Organization & Design, The Hardware/Software Interface - Third Edition

2. Computer Organization Layout I/O systemInstr. Set Proc. Digital Design Circuit Design Datapath & Control CPSC 414 Compiler Operating System Application Firmware  Coordination of many levels of abstraction  Under a rapidly changing set of forces

3. Computer Architecture Applications Operating Systems Technology (a =  F/m) Programming Languages History cleverness Forces on computer architecture

4. The big picture Since 1946 all computers have had 5 components Memory ROM DRAM SRAM Cache Processor Input keyboard mouse disk Output display printer Control ‘brain’ Datapath ‘brawn’

5. What is the significance of Computer Architecture? It impacts every other aspect of computer/electrical engineering and computer science. It’s exciting! Microprocessor performance growth “unmatched by other industries” [John Crawford, Intel fellow] Processor speed has doubled every 18 months (1982-1996) — Cars would travel at 44,000 mph and get 16,000 miles/gal. — Air travel: L.A. to N.Y. in 22 seconds.

6. Single-Electron Transistor Itanium (~ 2 billion Transistors) Computer architecture is becoming more important as computer technology continues to advance. What is the significance of Computer Architecture?

7. If you want to call yourself a “computer scientist” Programmers and computer scientists who seek to build competitive versions of compilers, operating systems, databases and even applications will need to increase their knowledge of computer architecture and organization: - interface between the software and hardware - performance of a program - hardware techniques that affect performance Why study Computer Architecture covered in CPEN315 CPSC330 and CPEN414?

8. What is “Computer Architecture”? Computer Architecture = Instruction Set Architecture + Machine Organization + …..

9. The Instruction Set: a Critical Interface instruction set software hardware

10. Instruction Set (IS) Architecture - continued A very important abstraction interface between hardware and low-level software standardizes instructions, machine language bit patterns etc. IS includes anything programmers need to know to make machines language program work correctly including instructions, registers, memory access, I/O devices, etc. Instruction set architectures: 80x86/Pentium/K6, DEC Alpha, MIPS, SPARC (Scalable Processor Architecture), HP workstations

11. From a high-level language to the language of the hardware Control Signal Specification Machine Interpretation °°°° High Level Language Program Assembly Language Program Machine Language Program Compiler Assembler temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw$15,0($2) lw$16,4($2) sw$16,0($2) sw$15,4($2) 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 ALUOP[0:3] <= InstReg[9:11] & MASK

12. RISC Characteristics: Uniform instruction format, with the opcode in the same bit positions in every instruction, demanding less decoding. Identical general purpose registers, allowing any register to be used in any context, simplifying compiler design (although normally separate floating point registers) Simple addressing modes. Complex addressing performed via sequences of arithmetic and/or load- store operations

13. RISC Instruction Format R-type: add $t3, $t2, $t6 I-type: addi $t2, $t3, 6 based or indexed addressing: lw $t2, 4($t0) -Load word at RAM address ($t0+4) into register $t2 -"4" gives offset from address in register $t0

14. RISC Instruction Format - continued based or indexed addressing: sw $t2, -12($t0) - store word in register $t2 into RAM at address ($t0 - 12) - negative offsets are fine Jumps j target # unconditional jump to program label target jr $t3 # jump to address contained in $t3 ("jump register")

15. Simple datapath with control unit op rd rt rs

16. Mapping Control to Hardware PLA structure Let’s try Opcode = 000000 What type of instruction format?

17. Datapath & Control phases of R-type instruction Instruction “fetch”ed & PC incremented Instruction decoded Register read of source arguments ALU op excuted Data written back to register

18. Datapath & Control flow of ‘load’ instruction Base register $t2 Offset Effective address $t2 + offset Destination register $t1 Data to load into $t1 Control Signal “Regdest” lw $t1, offset($t2) rt rs

19. Datapath & Control flow of ‘load’ instruction lw $t1, offset($t2) Instruction “fetch”ed & PC incremented Instruction decoded Register read of source argument Base register $t2 & offset ALU op excuted ALU computes sum value in $t2 and offset as address for data memory Data from memory written back to register

20. Datapath & Control flow of ‘branch equal’ instruction Register read of source arguments ALU op excuted subtract operation Instruction “fetch”ed & PC incremented Determine whether PC + 4 or branch destination address is written into the PC. MUX is set based on the zero output of the ALU

21. All previous slides have shown single cycle implementations Each instruction can complete within a single clock cycle  CPI = 1 But… the clock cycle is determined by the longest possible path in the machine. Which is the longest instruction? Hint: it uses 5 functional units in series: the instruction memory, the register file, the data memory, and the register file. Not optimal for all instructions; must use slower clock. Alternatives: 1. Multi-cycle implementation 2. Pipeline implementation Datapath & Control single cycle implementations