2. CS35101 Computer Architecture Spring 2006 Week 1 Slides adapted from: Mary Jane Irwin (www.cse.psu.edu/~mji)www.cse.psu.edu/~mji Course url: www.cs.psu.edu/~cg331www.cs.psu.edu/~cg331 [Adapted from Dave Patterson’s UCB CS152 slides]

4. Course Administration  Instructor:Paul J Durand durand@cs.kent.edu http://www.cs.kent.edu/~durand durand@cs.kent.edu http://www.cs.kent.edu/~durand  Labs:Accounts on loki or neptune  Texts:Computer Organization and Design: The Hardware/Software Interface, Third Edition, Patterson and Hennessy

5. Course Goals and Structure  Introduction to the major components of a computer system, how they function together in executing a program, how they are designed. l MIPS assembler programming using the spim system

6. spim Assembler and Simulator  spim is a self-contained assembler and simulator for the MIPS R2000/R3000 l It provides a simple assembler, debugger and a simple set of operating system services l It implements both a simple, terminal-style interface and a visual windowing interface  Available as l xspim on unix -installed on the CS unix machines loki, hermes, neptune, poseidon l PCSpim on Windows -can be downloaded and installed on your own PC from www.cs.wisc.edu/~larus/SPIM/pcspim.exe l Sorry, there is no Macintosh version of spim

7. Head’s Up  This week’s material l Course introduction -Reading assignment – PH 1.1 through 1.3 and A.9 through A.10 (on cd)  Reminders l Make sure your unix account is operational; change your password to something you can remember and that is secure (must be six to eight alphanumeric characters) l Check out the course homepage (www.cs.kent.edu/~durand)  Next week’s material l Introduction to MIPS assembler -Reading assignment - PH 2.1 through 2.7, omit 2.6

8. What You Should Already Know  How to write, compile and run programs in a higher level language (C, C++, Java, …)  How to create, organize, and edit files and run programs on Unix  How to represent and operate on positive and negative numbers in binary form (two’s complement, sign magnitude, etc.)  Logic design l How to design combinational components (Boolean algebra, logic minimization, decoders and multiplexors)

9. Below the Program  High-level language program (in C) swap (int v[], int k) (int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; )  Assembly language program (for MIPS) swap:sll$2, $5, 2 add$2, $4,$2 lw$15, 0($2) lw$16, 4($2) sw$16, 0($2) sw$15, 4($2) jr$31  Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000...

10. Below the Program  High-level language program (in C) swap (int v[], int k) (int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; )  Assembly language program (for MIPS) swap:sll$2, $5, 2 add$2, $4,$2 lw$15, 0($2) lw$16, 4($2) sw$16, 0($2) sw$15, 4($2) jr$31  Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000... C compilerassembler

11. Advantages of Higher-Level Languages  Higher-level languages  As a result, very little programming is done today at the assembler level

12. Advantages of Higher-Level Languages  Higher-level languages  As a result, very little programming is done today at the assembler level l Allow the programmer to think in a more natural language and for their intended use (Fortran for scientific computation, Cobol for business programming, Lisp for symbol manipulation, …) l Improve programmer productivity – more understandable code that is easier to debug and validate l Improve program maintainability l Allow programmers to be independent of the computer on which they are developed (compilers and assemblers can translate high-level language programs to the binary instructions of any machine) l Emergence of optimizing compilers that produce very efficient assembly code optimized for the target machine

13. Machine Organization  Capabilities and performance characteristics of the principal Functional Units (FUs) l e.g., register file, ALU, multiplexors, memories,...  The ways those FUs are interconnected l e.g., buses  Logic and means by which information flow between FUs is controlled  The machine’s Instruction Set Architecture (ISA)  Register Transfer Level (RTL) machine description

14. Major Components of a Computer Processor Control Datapath Memory Devices Input Output

15. Impacts of Advancing Technology  Processor l logic capacity:increases about 30% per year l performance:2x every 1.5 years  Memory l DRAM capacity:4x every 3 years l memory speed:1.5x every 10 years l cost per bit:decreases about 25% per year  Disk l capacity:increases about 60% per year

16. Example: Growth in DRAM Chip Capacity

17. Below the Program C compilerassembler one-to-many one-to-one  High-level language program (in C) swap (int v[], int k)...  Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31  Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000

18. Below the Program C compilerassembler one-to-many one-to-one  High-level language program (in C) swap (int v[], int k)...  Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31  Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000

19. Input Device Inputs Object Code Processor Control Datapath Memory Devices Input Output 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000

20. Object Code Stored in Memory Processor Control Datapath Memory Devices Input Output 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000

21. Processor Fetches an Instruction Processor Control Datapath Memory Devices Input Output 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 Processor fetches an instruction from memory Where does it fetch from?

22. Control Decodes the Instruction Processor Control Datapath Memory Devices Input Output 000000 00100 00010 0001000000100000 Control decodes the instruction to determine what to execute

23. Datapath Executes the Instruction Processor Control Datapath Memory Devices Input Output contents Reg #4 ADD contents Reg #2 results put in Reg #2 Datapath executes the instruction as directed by control 000000 00100 00010 0001000000100000

24. Processor Organization  Control needs to have the l Ability to input instructions from memory l Logic and means to control instruction sequencing l Logic and means to issue signals that control the way information flows between datapath components l Logic and means to control what operations the datapath’s functional units perform  Datapath needs to have the l Components - functional units (e.g., adder) and storage locations (e.g., register file) - needed to execute instructions l Components interconnected so that the instructions can be accomplished l Ability to load data from and store data to memory Where does it load and store from and to?

25. What Happens Next? Processor Control Datapath Memory Devices Input Output 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000

26. What Happens Next? Processor Control Datapath Memory Devices Input Output 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 FetchDecodeExec

27. Output Data Stored in Memory Processor Control Datapath Memory Devices Input Output 00000100010100000000000000000000 00000000010011110000000000000100 00000011111000000000000000001000 At program completion the data to be output resides in memory

28. Output Device Outputs Data Processor Control Datapath Memory Devices Input Output 00000100010100000000000000000000 00000000010011110000000000000100 00000011111000000000000000001000

29. The Instruction Set Architecture instruction set architecture software hardware The interface description separating the software and hardware. Stopped here 1/19

30. MIPS R3000 Instruction Set Architecture  Instruction Categories l Load/Store l Computational l Jump and Branch l Floating Point -coprocessor l Memory Management l Special R0 - R31 PC HI LO OP rs rt rdsafunct rs rt immediate jump target  3 Instruction Formats: all 32 bits wide Registers Q: How many already familiar with MIPS ISA?

31. How Do the Pieces Fit Together? I/O systemInstr. Set Proc. Compiler Operating System Application Digital Design Circuit Design Instruction Set Architecture Firmware  Coordination of many levels of abstraction  Under a rapidly changing set of forces  Design, measurement, and evaluation Memory system Datapath & Control