Counters Mano & Kime Sections 5-4, 5-5. Counters Ripple Counter Synchronous Binary Counters –Design with D Flip-Flops –Design with J-K Flip-Flops Counters.

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Presentation transcript:

Counters Mano & Kime Sections 5-4, 5-5

Counters Ripple Counter Synchronous Binary Counters –Design with D Flip-Flops –Design with J-K Flip-Flops Counters in VHDL

Counters ---

A 4-bit Ripple Counter Recall... Less Significant Bit output is Clock for Next Significant Bit! (Clock - active low)

J-K Flip-Flop from a D Flip-Flop D Q = J & !Q # !K & Q D Q = Q D Q = 0 D Q =!Q # Q = 1 D Q = !Q

Counters Ripple Counter Synchronous Binary Counters –Design with D Flip-Flops –Design with J-K Flip-Flops Counters in VHDL

CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter

s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q Q2.D Q2.D = !Q2 & Q1 & Q0 # Q2 & !Q1 # Q2 & !Q0

s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q Q1.D Q1.D = !Q1 & Q0 # Q1 & !Q0

s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q Q0.D Q0.D = ! Q0

CUPL Simulation Output File

CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D 3-Bit Down Counter

Q2 Q1 Q Q2.D Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0 s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D

3-Bit Down Counter Q2 Q1 Q Q1.D Q1.D = !Q1 & !Q0 # Q1 & Q0 s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D

3-Bit Down Counter Q2 Q1 Q Q0.D Q0.D = ! Q0 s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D

Up-Down Counter Up-Down Counter Q0 Q1 Q2 clock UD UD = 0: count up UD = 1: count down

Up-Down Counter UD Q2 Q1 Q0 Q2.D Q1.D Q0.D UD Q2 Q1 Q0 Q2.D Q1.D Q0.D Up-CounterDown-Counter

UD Q2 Q1 Q Up-Down Counter Make Karnaugh maps for Q2.D, Q1.D, and Q0.D

Counters Ripple Counter Synchronous Binary Counters –Design with D Flip-Flops –Design with J-K Flip-Flops Counters in VHDL

J-K Flip Flop Design of a Binary Up Counter Synchronous Binary Counters

J-K Flip Flop Design of a Binary Up Counter Synchronous Binary Counters

J-K Flip Flop Design of a Binary Up Counter Synchronous Binary Counters

J-K Flip Flop Design of a Binary Up Counter Synchronous Binary Counters

4 - Bit Counter Logic Diagram

Counters Ripple Counter Synchronous Binary Counters –Design with D Flip-Flops –Design with J-K Flip-Flops Counters in VHDL

4-Bit Binary Counter with Reset