1. 1 Sequential logic networks I. Motivation & Examples  Output depends on current input and past history of inputs.  “State” embodies all the information about the past needed to predict current output based on current input. –State variables, one or more bits of information.  If the current State of the circuit is known at time t, what is the state of the circuit at time (t+1) Answer: the next state depends on current state and input

2. 2 Sequential logic networks  State table –For each current-state, specify next-states as function of inputs –For each current-state, specify outputs as function of inputs  State diagram –Graphical version of state table I. Motivation & Examples Describing sequential circuit Example 1: TV channel control Let the channel # represent the state of the circuit Input are up/down on the channel control 123499 … uuuuu ddddd on u: up d: down

3. 3 Sequential logic networks I. Motivation & Examples Example 2: A sequential process that inputs an n-bit binary string and outputs 1 if the string contains an even number of 1’s 1 (final output) 01111 SLN 0 (final output) 0111 SLN What represents the state of the circuit? Case1: State as the number of 1’s read so far (possibly infinite # of states) Case 2: Two states E and O E (even): if the # of 1’s read so far is even O (odd) if the # of 1’s read so far is odd

4. 4 Sequential logic networks I. Motivation & Examples Example 2: State Diagram for Case 1 1232n … 0 1/01/11/01/11/0 4 1/1 0/0 0/1 Example 2: State Diagram for Case 2 InputOutput OE 1/0 0/1 1/1 0/0 InputOutput

5. 5 Sequential logic networks I. Motivation & Examples Example 2: State Diagram for Case 2 OE 1/0 0/1 1/1 0/0 InputOutput Better design Has less states

6. 6 Sequential logic networks I. Motivation & Examples Example 3: Discuss sequential n-bits comparator Compare two n-bits numbers X=[Xn-1, …, X0], Y=[Yn-1, …, Y0] Output 1 if X>Y Use the basic 1-bit comparator designed in class Xn-1Xn-2Xn-3X2X1X0 Shift right 1-bit Comparator Ci Yn-1Yn-2Yn-3Y2Y1Y0 Shift right Fi Xi Fi-1 Yi Operation controlled by a clock to decide:.when to shift input data.when output Fi is stable...

7. 7 Sequential logic networks I. Motivation & Examples Example 4: Discuss sequential n-bits adder Add two n-bits numbers X=[Xn-1, …, X0], Y=[Yn-1, …, Y0] Output S=X+Y where [Sn,Sn-1,…,S0] Use the basic 1-bit adder with carry in and carry out Xn-1Xn-2Xn-3X2X1X0 Shift right 1-bit Full adder Ci Yn-1Yn-2Yn-3Y2Y1Y0 Shift right Ci Xi Ci-1 Yi Operation controlled by a clock to decide:.when to shift input data.when output are ready Shift right Sn-1Sn-2S2S1S0... Sn

8. 8 Sequential logic networks Clock signals  Sequential circuit are controlled by a clock signal  Very important with most sequential circuits –State variables change state at clock edge. II. General Representation

9. 9 Sequential logic networks General diagram of sequential circuit  Sequential circuit are controlled by a clock signal  Very important with most sequential circuits –State variables change state at clock edge. II. General Representation SLN Memory components Input i0 i1 … in Output o0 o1 … om Current statesNext states State variables: s0,s1, …sk Feedback

10. 10 Sequential logic networks Some important questions  How to represent the states of a sequential circuit?  How to memorize the (current and next) states?  How to determine the next of the circuit?  How to determine the outputs –as a function F(state) of current state only? –as a function F(input,state) of both input and current state? *The concept of STATE is very important II. General Representation

11. 11 Sequential logic networks Memory component  How do we represent the states?  Memory component are used as state variables –Goal: Memorize the current state of the circuit –How are memory components implemented?  Latch, Flip-flop are 1-bit memory component II. General Representation

12. 12 Sequential logic networks Bistable element  The simplest sequential circuit  Two states –One state variable, say, Q (QN or Q_L the complement of Q) HIGHLOW HIGH III. Basic memory component

13. 13 Sequential logic networks Bistable element  The simplest sequential circuit  Two states –One state variable, say, Q LOWHIGH LOW III. Basic memory component

14. 14 Sequential logic networks Bistable element: Analog analysis  Assume pure CMOS thresholds, 5V rail  Theoretical threshold center is 2.5 V III. Basic memory component

15. 15 Sequential logic networks Bistable element: Analog analysis  Assume pure CMOS thresholds, 5V rail  Theoretical threshold center is 2.5 V 2.5 V III. Basic memory component

16. 16 Sequential logic networks Bistable element: Analog analysis  Assume pure CMOS thresholds, 5V rail  Theoretical threshold center is 2.5 V 2.5 V 2.0 V 4.8 V 2.5 V2.51 V4.8 V0.0 V 5.0 V III. Basic memory component

17. 17 Sequential logic networks Bistable element: summary  If (Q=0), then input to Not gate 2 is 0 ==> Output of Not gate 2 is 1 (Q_L =1) ==> The input of Not gate 1 is 1, so output of Not gate 1 is 0 ==> Stable output (Q=0) and (Q_L = 1)  If (Q=1), then input to Not gate 2 is 1 ==> Output of Not gate 2 is 0 (Q_L =0) ==> The input of Not gate 1 is 0, so output Not gate 1 is ==> Stable output (Q=1) and (Q_L = 0) II. General Representation 1 2

18. 18 Sequential logic networks S-R Latch….  How to control it? –Screwdriver –Control inputs  S-R latch III. Basic memory component Contradiction!!!!

19. 19 Sequential logic networks S-R Latch…. III. Basic memory component Set operation: SR 00 ----> 10, set the device output to Q=1 regardless of current value of Q Reset operation: SR 00 ----> 01, set the device output to Q=0 regardless of current value of Q Hold operation: SR 10 ----> 00 or 01 ----> 00, Device output are the same as last output values Only one input value changes Possible input changes: SR: 00 ---> 01 ---> 00 ---> 10 ---> 00 …. Input SR = 11 is not allowed ( Both NOR gates output 0, i.e Q=Q’=0 )

20. 20 Sequential logic networks S-R latch operation III. Basic memory component

21. 21 Sequential logic networks S-R latch timing parameters  Propagation delay  Minimum pulse width III. Basic memory component Progation delay Minimum time to maintain signal at 1

22. 22 Sequential logic networks S-R latch symbols

23. 23 Sequential logic networks S-R latch with enable III. Basic memory component

24. 24 Sequential logic networks Sequential network architecture (revisited) III. Basic memory component Output o1 om SLN...... Input i1 in M1... Mk Components Mi are latches/Flip flops Operation rules: Memory components Mi must be in stable state before input changes Only one input of the component Mi can change at a time

25. 25 Sequential logic networks Charcteristics equation of S-R latch III. Basic memory component Definition: The characteristic equation specifies a flip-flop next state as a function of its current state and inputs Notation: Let q represent the current state of the flip-flop and Q its next S R q Q 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 1 1 X Q=q Q=0 Q= 1 X Not allowed Hold Reset Set Characteristics table

26. 26 Sequential logic networks Charcteristics table (other representation) III. Basic memory component S R Q 0 0 1 1 0 1 q 0 1 X Q=q Q=0 Q= 1 Not allowed Hold Reset Set Characteristics table

27. 27 Sequential logic networks Charcteristics equation of S-R latch III. Basic memory component Use the characteristics table to get an excitation map of the flip flop S R q Q 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 1 1 X Q=q Q=0 Q= 1 X Characteristics table SR q 0 1 00011110 X X 1 1 1 Q Use K-map method to derive the characteristics equation: Q = S + R’q

28. 28 Sequential logic networks Excitation table of SR flip flop III. Basic memory component The excitation table describes the input values of S and R that cause the corresponding transitions (q ---> Q) from current to next state Types of transitions: q --->Q 0 ---> 0 0 ---> 1 1 ---> 0 1 ---> 1 Excitation table of S R latch q ---> Q SR 0 ---> 0 0 ---> 1 1 ---> 0 1 ---> 1 0X 10 01 X0 0 0 to hold current value 0 1 to reset Q=0 OR 0 0 to hold current value 1 0 to set Q=1 OR

29. 29 Sequential logic networks JK Flip- Flop III. Basic memory component Recall: In SR flip flop, both input S, R cannot be 1 (SR=11) This restriction is removed in a JK flip flop. The behavior of the JK flip flop is as follows: J K q Q 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 1 1 1 Q=q Q=0 Q= 1 0 Q = Q’ (Toggle) Hold Reset Set Characteristics table

30. 30 Sequential logic networks Charateristics of JK flip flop (other representation) III. Basic memory component C J K Q 1 0 0 1 0 1 1 1 0 1 1 1 q 0 1 q' Q =q Q =0 Q = 1 Q = q’ (Toggle) Hold Reset Set Characteristics table Characteristics table Characteristics table ( Clocked JK flip flop ) 0 x x Disabled J K Q 0 0 1 1 0 1 q 0 1 q' Q =q Q =0 Q = 1 Q = q’ (Toggle) Hold Reset Set

31. 31 Sequential logic networks Charcteristics equation of Jk Flip flop III. Basic memory component Use the characteristics table to get an excitation map of the flip flop Characteristics table JK q 0 1 00011110 1 0 1 1 1 Q Use K-map method to derive the characteristics equation: Q = Jq’ + Kq J K q Q 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 1 1 1 Q=q Q=0 Q= 1 0 Q = Q’ 0 0 0

32. 32 Sequential logic networks Excitation table of JK flip flop III. Basic memory component The excitation table describes the input values of S and R that cause the corresponding transitions (q ---> Q) from current to next state Types of transitions: q --->Q 0 ---> 0 0 ---> 1 1 ---> 0 1 ---> 1 Excitation table of JK flip flop q ---> Q JK 0 ---> 0 0 ---> 1 1 ---> 0 1 ---> 1 0X 1X X1 X0 0 0 to hold current value 0 1 to reset Q=0 OR 0 0 to hold current value 1 0 to set Q=1 OR

33. 33 Sequential logic networks Excitation table of JK flip flop III. Basic memory component The excitation table describes the input values of S and R that cause the corresponding transitions (q ---> Q) from current to next state Types of transitions: q --->Q 0 ---> 0 0 ---> 1 1 ---> 0 1 ---> 1 Excitation table of JK flip flop q ---> Q JK 0 ---> 0 0 ---> 1 1 ---> 0 1 ---> 1 0X 1X X1 X0 0 0 to hold current value 0 1 to reset Q=0 OR 0 0 to hold current value 1 0 to set Q=1 OR

34. 34 Sequential logic networks JK Flip flop Symbols III. Basic memory component J K Q QN J K Q Q J K Q CK J K Q QN CK Clocked JK Flip flop

35. 35 Sequential logic networks D Flip- flop ( Delay flip flop) III. Basic memory component This flip flop has only one control input. The D flip flop simply retains its input between clock pulses D q Q 0 0 1 1 0 1 0 0 1 1 Q=d Characteristics table C D Q 1 0 1 Characteristics table Characteristics table ( Clocked D flip flop ) 0 x 0 1 Q=d Disabled

36. 36 Sequential logic networks Charcteristics equation of D Flip flop III. Basic memory component Use the characteristics table to get an excitation map of the flip flop Characteristics table Characteristics equation: Q = D D q Q 0 0 1 1 0 1 0 1 0 1

37. 37 Sequential logic networks D Flip flop Symbols III. Basic memory component DQ QN DQ Q DQ CK DQ QN CK Clocked JK Flip flop

38. 38 Sequential logic networks D latch III. Basic memory component

39. 39 Sequential logic networks D-latch operation III. Basic memory component

40. 40 Sequential logic networks D-latch timing parameters  Propagation delay (from C or D)  Setup time (D before C edge)  Hold time (D after C edge) III. Basic memory component

41. 41 Sequential logic networks Edge-triggered D flip-flop behavior

42. 42 Sequential logic networks Edge-triggered D flip-flop behavior III. Basic memory component

43. 43 Sequential logic networks D flip-flop timing parameters  Propagation delay (from CLK)  Setup time (D before CLK)  Hold time (D after CLK) III. Basic memory component

44. 44 Sequential logic networks IV. Counters  A counter is a sequential-circuit that generates a predetermined number sequence over and over again  A counter can be used as –a digital clock –special sequence generator –program counter –pulse counter Definitions

45. 45 Sequential logic networks Examples IV. Counters 0123456789 0123456 00011110 000000010011001001100100

46. 46 Sequential logic networks IV. Counters  Counters are often implemented by Flip flops. They are –synchronous if all flip flops are clocked by the same signal –ripple (asynchronous) individual flip flop are clocked at different times  Counters may be classified by other characteristics: –mod N counter or divide-by- N counter, if counter has N distinct states (State = a number of the counted sequence) –by the number of fli flops in the counter: n bit counter –Other types of counter:  binary up (or down) counter : successive states represent an increasing binary count 00 --> 01 --> 10 --> 11 --> 00 ……..  gray code binary counter 00 --> 01 ---> 11 ---> 10 ---> 00 Types of counters

47. 47 Sequential logic networks IV. Counters  Problem Statement Design a sequential device to generate the sequence 0, 1, 2, 3 over and over again  There are 4 distinct states (divide-by-4) counter  Encode the four states as follows; 0 encoded by 00 1 encoded by 01 2 encoded by 10 3 encoded by 11  Represent each binary bit of a code by a flip flop (in this example, let us use JK flip flops to design the counter) Intuitive Design of a counter 00011011

48. 48 Sequential logic networks IV. Counters  Flip flop 0 changes state at every clock pulse  Flip flop 1 changes states every two clock pulses Intuitive Design of a counter 00 01 10 11 00 01 10 11 Flip flop 1 Flip flop 0 State transition flip flop 0

49. 49 Sequential logic networks IV. Counters Design using JK flip flops for states 0 and 1 of the counter Intuitive Design of a counter J K Q QN CK J K Q QN CK 1 1 EN S0 S1 S1S0 : 00 --> 01 --> 10 --> 11 --> 00 …….

50. 50 Sequential logic networks IV. Counters Design using JK flip flops Intuitive Design of a 4 bit binary counter S3S2S1S0 : 0000 --> 0001 --> 0010 --> 0011 --> 0100 --> 0101 … --> 1111 --> 0000  There are 16 states  design requires four flip flops  Synchronous design, all flip flops clocked by the same signal  S0 Changes state (toggles) every clock pulse  S1 Changes state (toggles) when S0 = 1  S2 Changes state (toggles) when S1=1 and S0 = 1  S3 Changes state (toggles) when S2=1, S1=1 and S0=1

51. 51 Sequential logic networks IV. Counters Design using JK flip flops Intuitive Design of a 4 bit binary counter J K Q QN CK J K Q QN CK J K Q QN CK J K Q QN CK EN S3S2S1S0 1 1

52. 52 Sequential logic networks State-machine structure (Mealy) typically edge-triggered D flip-flops output depends on state and input V. Sequential network design

53. 53 Sequential logic networks State-machine structure (Moore) output depends on state only typically edge-triggered D flip-flops V. Sequential network design

54. 54 Sequential logic networks Q Q’C D Q C S R Q C J K Characteristic Table S R q Q 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 01000100 1 -- J K q Q 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 01000100 11101110 D q Q 0 0 1 1 0 1 00110011 Characteristic Equation Q = D SR q 00 01 11 10 0101 1 d d1 1 Q = S + R’q JK q 00 01 11 10 0101 1 1 1 1 Q = Jq’ + K’q Transition Table (Excitation Table) q  Q D 0  0 0  1 1  0 1  1 01010101 q  Q S R 0  0 0  1 1  0 1  1 0 d 1 0 0 1 d 0 q  Q J K 0  0 0  1 1  0 1  1 0 d 1 d d 1 d 0 D Flip flopS-R Flip flopJ-K Flip flop q : Current state Q : Next state V. Sequential network design Flip Flop : summary

55. 55 Sequential logic networks Characteristic table : For each input and state combination, define the next state of the flip flop Characteristic equation: Define the next state (Q) as a function of current state and input to the flip flop Transition table (excitation table): For each transition type, define the inputs that cause the transition V. Sequential network design Flip Flop : summary

56. 56 Sequential logic networks Synchronous state machine : Major design steps Step 1: Start from state diagram or word description Step 2: Construct a State/Output table Moore machine: one output per state (one output column) Mealy machine: One output per state and for each input combination (one output column per input combination) Step 3: Reduce the number of states in State/output table by removing redundant states (a state is redundant if for the same input combinations) it has the same next state and output as another state. Step4: Encode the states in binary (for n states, log 2 n bits are required). Each bit in the code represents a flip flop. Step5: Substitute corresponding binary codes to states in the State/Output table Step6: Separate the state table into flip flop next state maps (one map for each bit or flip flop) Step7: Use the flip flop next state map to derive flip flop excitation maps (this step depends on the type of flip flop used in the design) Step8: Use the flip flop excitation maps to determine excitation equations for the flip flop (these equations define the input logic of the flip flop) Step 9: Use the State/Output table to define the output logic circuit Step10: Draw the circuit, including flip flop, flip flop input circuits and output circuit. V. Sequential network design Major design steps