Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 7 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Gate-Level Power Optimization Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 72 Components of Power Dynamic Dynamic Signal transitions Signal transitions Logic activity Glitches Short-circuit Short-circuit Static Static Leakage Leakage

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 73 Power of a Transition V DD Ground CLCL R R Dynamic Power = C L V DD 2 /2 + P sc ViVi VoVo i sc

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 74 Dynamic Power Each transition of a gate consumes CV 2 /2. Each transition of a gate consumes CV 2 /2. Methods of power saving: Methods of power saving: Minimize load capacitances Minimize load capacitances Transistor sizing Library-based gate selection Reduce transitions Reduce transitions Logic design Glitch reduction

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 75 Glitch Power Reduction Design a digital circuit for minimum transient energy consumption by eliminating hazards Design a digital circuit for minimum transient energy consumption by eliminating hazards

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 76 Theorem 1 For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition. For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition. Output logic state changes One transition is necessary Output logic state unchanged No transition is necessary

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 77 Event Propagation Path P1 P2 Path P3 Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 78 Inertial Delay of an Inverter d HL d LH d HL +d LH d = ──── 2 V in V out time

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 79 Multi-Input Gate Delay d < DPD ABAB C ABCABC d dHazard or glitch DPD DPD: Differential path delay

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 710 Balanced Path Delays Delay d < DPD ABAB C ABCABC d No glitch DPD Delay buffer

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 711 Glitch Filtering by Inertia Delay d > DPD ABAB C ABCABC Filtered glitch DPD

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 712 Given that events occur at the input of a gate with inertial delay d at times, t 1 ≤... ≤ t n, the number of events at the gate output cannot exceed Given that events occur at the input of a gate with inertial delay d at times, t 1 ≤... ≤ t n, the number of events at the gate output cannot exceed Theorem 2 min ( n, 1 + ) t n – t d t n - t 1 t n - t 1 t 1 t 2 t 3 t n t 1 t 2 t 3 t n time time

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 713 Minimum Transient Design Minimum transient energy condition for a Boolean gate: Minimum transient energy condition for a Boolean gate: | t i - t j | < d Where t i and t j are arrival times of input events and d is the inertial delay of gate

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 714 Balanced Delay Method All input events arrive simultaneously All input events arrive simultaneously Overall circuit delay not increased Overall circuit delay not increased Delay buffers may have to be inserted Delay buffers may have to be inserted No increase in critical path delay

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 715 Hazard Filter Method Gate delay is made greater than maximum input path delay difference Gate delay is made greater than maximum input path delay difference No delay buffers needed (least transient energy) No delay buffers needed (least transient energy) Overall circuit delay may increase Overall circuit delay may increase

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 716 Designing a Glitch-Free Circuit Maintain specified critical path delay. Maintain specified critical path delay. Glitch suppressed at all gates by Glitch suppressed at all gates by Path delay balancing Path delay balancing Glitch filtering by increasing inertial delay of gates or by inserting delay buffers when necessary. Glitch filtering by increasing inertial delay of gates or by inserting delay buffers when necessary. A linear program optimally combines all objectives. A linear program optimally combines all objectives. Delay D Path delay = d1 Path delay = d2 |d1 – d2| < D

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 717 Problem Complexity Number of paths in a circuit can be exponential in circuit size. Number of paths in a circuit can be exponential in circuit size. Considering all paths through enumeration is infeasible for large circuits. Considering all paths through enumeration is infeasible for large circuits. Example: c880 has 6.96M path constraints. Example: c880 has 6.96M path constraints.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 718 Define Timing Variables d Gate delay. d i Gate delay. Define two per gate output: Define two timing window variables per gate output: t i Earliest time of signal transition at gate i. t i Earliest time of signal transition at gate i. T i Latest time of signal transition at gate i. T i Latest time of signal transition at gate i. Glitch suppression constraint: T – t < d Glitch suppression constraint: T i – t i < d i t 1, T 1 t n, T n t i, T i Reference: T. Raja, Master’s Thesis, Rutgers Univ., didi

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 719 Linear Program Variables: gate and buffer delays Variables: gate and buffer delays Objective: minimize number of buffers Objective: minimize number of buffers Subject to: overall circuit delay constraint for all input-output paths Subject to: overall circuit delay constraint for all input-output paths Subject to: minimum transient condition for all multi-input gates Subject to: minimum transient condition for all multi-input gates

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 720 An Example: Full Adder add1b 1 1 Critical path delay =

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 721 Linear Program Gate variables: d 4... d 12 Gate variables: d 4... d 12 Buffer delay variables: d d 29 Buffer delay variables: d d 29 Window variables: t 4... t 29 and T T 29 Window variables: t 4... t 29 and T T 29

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 722 Multiple-Input Gate Constraints For Gate 7: T 7 ≥ T 5 + d 7 t 7 ≤ t 5 + d 7 d 7 > T 7 - t 7 ; T 7 ≥ T 6 + d 7 t 7 ≤ t 6 + d 7

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 723 Single-Input Gate Constraints T 16 + d 19 = T 19 t 16 + d 19 = t 19 Buffer 19:

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 724 Critical Path Delay Constraints T 11 ≤ maxdelay T 12 ≤ maxdelay maxdelay is specified

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 725 AMPL Solution: maxdelay = Critical path delay =

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 726 AMPL Solution: maxdelay = Critical path delay =

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 727 AMPL Solution: maxdelay ≥ Critical path delay =

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 728 Four-Bit ALU maxdelay Buffers inserted Maximum Power Savings (zero-buffer design): Peak = 33 %, Average = 21 %

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 729 ALU4: Original and Low-Power

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 730 Benchmark Circuits Circuit ALU4 C880 C6288 c7552 Max-delay (gates) No. of Buffers Average Peak Normalized Power

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 731 C7552 Circuit: Spice Simulation Power Saving: Average 58%, Peak 68%

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 732 References R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco: The Scientific Press, R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco: The Scientific Press, M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10 th Int’l Conf. VLSI Design, Jan. 1997, pp V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10 th Int’l Conf. VLSI Design, Jan. 1997, pp V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Proc. 12 th Int’l Conf. VLSI Design, Jan. 1999, pp V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Proc. 12 th Int’l Conf. VLSI Design, Jan. 1999, pp M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” Proc. 16 th Int’l Conf. VLSI Design, Jan. 2003, pp T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” Proc. 16 th Int’l Conf. VLSI Design, Jan. 2003, pp T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay CMOS Logic for Low Power Design,” Proc. 18 th Int’l Conf. VLSI Design, Jan. 2005, pp T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay CMOS Logic for Low Power Design,” Proc. 18 th Int’l Conf. VLSI Design, Jan. 2005, pp

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 733 Components of Power Dynamic Dynamic Signal transitions Signal transitions Logic activity Logic activity Glitches Glitches Short-circuit Short-circuit Static Static Leakage Leakage

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 734 Subthreshold Conduction V gs – V th -V ds I ds =I 0 exp( ───── ) × (1– exp ── ) nV T V T Sunthreshold slope V V gs I ds 1mA 100μA 10μA 1μA 100nA 10nA 1nA 100pA 10pA V th Subthreshold region Saturation region

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 735 Thermal Voltage, v T V T = kT/q = 26 mV, at room temperature. When V ds is several times greater than V T V gs – V th I ds =I 0 exp( ───── ) nV T

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 736 Leakage Current Leakage current equals I ds when V gs = 0 Leakage current equals I ds when V gs = 0 Leakage current, I ds = I 0 exp(-V th /nV T ) Leakage current, I ds = I 0 exp(-V th /nV T ) At cutoff, V gs = V th, and I ds = I 0 At cutoff, V gs = V th, and I ds = I 0 Lowering leakage to 10 -b I 0 Lowering leakage to 10 -b I 0 V th = bnV T ln 10 = 1.5b × 26 ln 10 = 90b mV Example: To lower leakage to I 0 /1,000 Example: To lower leakage to I 0 /1,000 V th = 270 mV

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 737 Threshold Voltage V th = V t0 + γ[(Φ s +V sb ) ½ - Φ s ½ ] V th = V t0 + γ[(Φ s +V sb ) ½ - Φ s ½ ] V t0 is threshold voltage when source is at body potential (0.4 V for 180nm process) V t0 is threshold voltage when source is at body potential (0.4 V for 180nm process) Φ s = 2V T ln(N A /n i ) is surface potential Φ s = 2V T ln(N A /n i ) is surface potential γ = (2qε si N A ) ½ t ox /ε ox is body effect coefficient (0.4 to 1.0) γ = (2qε si N A ) ½ t ox /ε ox is body effect coefficient (0.4 to 1.0) N A is doping level = 8×10 17 cm -3 N A is doping level = 8×10 17 cm -3 n i = 1.45×10 10 cm -3 n i = 1.45×10 10 cm -3

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 738 Threshold Voltage, V sb = 1.1V Thermal voltage, V T = kT/q = 26 mV Thermal voltage, V T = kT/q = 26 mV Φ s = 0.93 V Φ s = 0.93 V ε ox = 3.9×8.85× F/cm ε ox = 3.9×8.85× F/cm ε si = 11.7×8.85× F/cm ε si = 11.7×8.85× F/cm t ox = 40 A o t ox = 40 A o γ = 0.6 V ½ γ = 0.6 V ½ V th = V t0 + γ[(Φ s +V sb ) ½ - Φ s ½ ] = 0.68 V V th = V t0 + γ[(Φ s +V sb ) ½ - Φ s ½ ] = 0.68 V

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 739 A Sample Calculation V DD = 1.2V, 100nm CMOS process V DD = 1.2V, 100nm CMOS process Transistor width, W = 0.5μm Transistor width, W = 0.5μm OFF device (V gs = V th ) leakage OFF device (V gs = V th ) leakage I 0 = 20nA/μm, for low threshold transistor I 0 = 20nA/μm, for low threshold transistor I 0 = 3nA/μm, for high threshold transistor I 0 = 3nA/μm, for high threshold transistor 100M transistor chip 100M transistor chip Power = (100×10 6 /2)(0.5×20×10 -9 A)(1.2V) = 600mW for all low-threshold transistors Power = (100×10 6 /2)(0.5×20×10 -9 A)(1.2V) = 600mW for all low-threshold transistors Power = (100×10 6 /2)(0.5×3×10 -9 A)(1.2V) = 90mW for all high-threshold transistors Power = (100×10 6 /2)(0.5×3×10 -9 A)(1.2V) = 90mW for all high-threshold transistors

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 740 Dual-Threshold Chip Low-threshold only for 20% transistors on critical path. Low-threshold only for 20% transistors on critical path. Leakage power = 600× ×0.8 Leakage power = 600× ×0.8 = = 192 mW

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 741 Dual-Threshold CMOS Circuit

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 742 Dual-Threshold Design To maintain performance, all gates on critical paths are assigned low V th. To maintain performance, all gates on critical paths are assigned low V th. Most other gates are assigned high V th. Most other gates are assigned high V th. But, some gates on non-critical paths may also be assigned low V th to prevent those paths from becoming critical. But, some gates on non-critical paths may also be assigned low V th to prevent those paths from becoming critical.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 743 Integer Linear Programming (ILP) to Minimize Leakage Power Use dual-threshold CMOS process Use dual-threshold CMOS process First, assign all gates low V th First, assign all gates low V th Use an ILP model to find the delay (T c ) of the critical path Use an ILP model to find the delay (T c ) of the critical path Use another ILP model to find the optimal V th assignment as well as the reduced leakage power for all gates without increasing T c Use another ILP model to find the optimal V th assignment as well as the reduced leakage power for all gates without increasing T c Further reduction of leakage power possible by letting T c increase Further reduction of leakage power possible by letting T c increase

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 744 ILP -Variables For each gate i define two variables. T i : the longest time at which the output of gate i can produce an event after the occurrence of an input event at a primary input of the circuit. T i : the longest time at which the output of gate i can produce an event after the occurrence of an input event at a primary input of the circuit. X i : a variable specifying low or high V th for gate i ; X i is an integer [0, 1], X i : a variable specifying low or high V th for gate i ; X i is an integer [0, 1], 1  gate i is assigned low V th, 1  gate i is assigned low V th, 0  gate i is assigned high V th.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 745 ILP - objective function minimize the sum of all gate leakage currents, given by I Li is the leakage current of gate i with low V th I Li is the leakage current of gate i with low V th I Hi is the leakage current of gate i with high V th I Hi is the leakage current of gate i with high V th Using SPICE simulation results, construct a leakage current look up table, which is indexed by the gate type and the input vector. Using SPICE simulation results, construct a leakage current look up table, which is indexed by the gate type and the input vector. Leakage power:

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 746 ILP - Constraints For each gate For each gate (1) (1) output of gate j is fanin of gate i (2) (2) Max delay constraints for primary outputs (PO) Max delay constraints for primary outputs (PO) (3) T max is the maximum delay of the critical path Gate j Gate i TjTj TiTi

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 747 ILP Constraint Example Assume all primary input (PI) signals on the left arrive at the same time. Assume all primary input (PI) signals on the left arrive at the same time. For gate 2, constraints are For gate 2, constraints are

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 748 ILP – Constraints (cont.) D Hi is the delay of gate i with high V th D Hi is the delay of gate i with high V th D Li is the delay of gate i with low V th D Li is the delay of gate i with low V th A second look-up table is constructed and specifies the delay for given gate type and fanout number. A second look-up table is constructed and specifies the delay for given gate type and fanout number.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 749 ILP – Finding Critical Delay T max can be specified or be the delay of longest path (T c ). T max can be specified or be the delay of longest path (T c ). To find T c, we change constraints (2) to an equation, assigning all gates low V th To find T c, we change constraints (2) to an equation, assigning all gates low V th Maximum T i in the ILP solution is T c. Maximum T i in the ILP solution is T c. If we replace T max with T c, the objective function minimizes leakage power without sacrificing performance. If we replace T max with T c, the objective function minimizes leakage power without sacrificing performance.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 750 Power-Delay Tradeoff

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 751 Power-Delay Tradeoff If we gradually increase T max from T c, leakage power is further reduced, because more gates can be assigned high V th. If we gradually increase T max from T c, leakage power is further reduced, because more gates can be assigned high V th. But, the reduction trends to become slower. But, the reduction trends to become slower. When T max = (130%) T c, the reduction about levels off because almost all gates are assigned high V th. When T max = (130%) T c, the reduction about levels off because almost all gates are assigned high V th. Maximum leakage reduction can be 98%. Maximum leakage reduction can be 98%.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 752 Leakage & Dynamic Power Optimization 70nm CMOS c7552 Benchmark 90 o C Leakage exceeds dynamic power Y. Lu and V. D. Agrawal, “CMOS Leakage and Glitch Minimization for Power- Performance Tradeoff,” Journal of Low Power Electronics (JOLPE), vol. 2, no. 3, pp , December 2006.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 753 Summary Leakage power is a significant fraction of the total power in nanometer CMOS devices. Leakage power is a significant fraction of the total power in nanometer CMOS devices. Leakage power increases with temperature; can be as much as dynamic power. Leakage power increases with temperature; can be as much as dynamic power. Dual threshold design can reduce leakage. Dual threshold design can reduce leakage. Reference: Y. Lu and V. D. Agrawal, “CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff,” J. Low Power Electronics, Vol. 2, No. 3, pp , December Access other paper at

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 754 Problem: Leakage Reduction Following circuit is designed in 65nm CMOS technology using low threshold transistors. Each gate has a delay of 5ps and a leakage current of 10nA. Given that a gate with high threshold transistors has a delay of 12ps and leakage of 1nA, optimally design the circuit with dual-threshold gates to minimize the leakage current without increasing the critical path delay. What is the percentage reduction in leakage power? What will the leakage power reduction be if a 30% increase in the critical path delay is allowed?

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 755 Solution 1: No Delay Increase Three critical paths are from the first, second and third inputs to the last output, shown by a dashed line arrow. Each has five gates and a delay of 25ps. None of the five gates on the critical path (red arrow) can be assigned a high threshold. Also, the two inverters that are on four-gate long paths cannot be assigned high threshold because then the delay of those paths will become 27ps. The remaining three inverters and the NOR gate can be assigned high threshold. These gates are shaded blue in the circuit. The reduction in leakage power = 1 – (4×1+7×10)/(11×10) = 32.73% Critical path delay = 25ps 5ps 12ps

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 756 Solution 2: 30% Delay Increase Several solutions are possible. Notice that any 3-gate path can have 2 high threshold gates. Four and five gate paths can have only one high threshold gate. One solution is shown in the figure below where six high threshold gates are shown with shading and the critical path is shown by a dashed red line arrow. The reduction in leakage power = 1 – (6×1+5×10)/(11×10) = 49.09% Critical path delay = 29ps 12ps 5ps