Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 1 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Introduction Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 12 Course Objectives Low-power is a current need in VLSI design. Low-power is a current need in VLSI design. Learn basic ideas, concepts, theory and methods. Learn basic ideas, concepts, theory and methods. Gain experience with techniques and tools. Gain experience with techniques and tools.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 13 Student Evaluation Homeworks (30%) ~ Four Homeworks (30%) ~ Four Class Project (30%) Class Project (30%) Student presentation (10%) Student presentation (10%) Final Exam (30%): Tuesday, December 11, 2007, 2:00 – 4:30PM, Broun 306. Final Exam (30%): Tuesday, December 11, 2007, 2:00 – 4:30PM, Broun 306.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 14 Power Consumption of VLSI Chips Why is it a concern?

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 15 ISSCC, Feb. 2001, Keynote “Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now. “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor....” Patrick P. Gelsinger Senior Vice President General Manager Digital Enterprise Group INTEL CORP.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 16 VLSI Chip Power Density Pentium® P Year Power Density (W/cm 2 ) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel 

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 17 SIA Roadmap for Processors (1999) Year Feature size (nm) Logic transistors/cm 2 6.2M18M39M84M180M390M Clock (GHz) Chip size (mm 2 ) Power supply (V) High-perf. Power (W) Source:

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 18 Recent Data Source:

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 19 Low-Power Design Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. Low-power design methods: Low-power design methods: Algorithms and architectures Algorithms and architectures High-level and software techniques High-level and software techniques Gate and circuit-level methods Gate and circuit-level methods Test power Test power

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 110 VLSI Building Blocks Finite-state machine (FSM) Finite-state machine (FSM) Bus Bus Flip-flops and shift registers Flip-flops and shift registers Memories Memories Datapath Datapath Processors Processors Analog circuits Analog circuits RF components RF components

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 111 Specific Topics in Low-Power Power dissipation in CMOS circuits Power dissipation in CMOS circuits Device technology Device technology Low-power CMOS technologies Low-power CMOS technologies Energy recovery methods Energy recovery methods Circuit and gate level methods Circuit and gate level methods Logic synthesis Logic synthesis Dynamic power reduction techniques Dynamic power reduction techniques Leakage power reduction Leakage power reduction System level methods System level methods Microprocessors Microprocessors Arithmetic circuits Arithmetic circuits Low power memory technology Low power memory technology Test Power Test Power Power estimation Power estimation

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 112 Some Examples

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 113 State Encoding for a Counter Two-bit binary counter: Two-bit binary counter: State sequence, 00 → 01 → 10 → 11 → 00 State sequence, 00 → 01 → 10 → 11 → 00 Six bit transitions in four clock cycles Six bit transitions in four clock cycles 6/4 = 1.5 transitions per clock 6/4 = 1.5 transitions per clock Two-bit Gray-code counter Two-bit Gray-code counter State sequence, 00 → 01 → 11 → 10 → 00 State sequence, 00 → 01 → 11 → 10 → 00 Four bit transitions in four clock cycles Four bit transitions in four clock cycles 4/4 = 1.0 transition per clock 4/4 = 1.0 transition per clock Gray-code counter is more power efficient. Gray-code counter is more power efficient. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston: Kluwer Academic Publishers (now Springer), 1998.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 114 Binary Counter: Original Encoding Present state Next state abAB A = a’b + ab’ B = a’b’ + ab’ ABAB a b CK CLR

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 115 Binary Counter: Gray Encoding Present state Next state abAB A = a’b + ab B = a’b’ + a’b ABAB a b CK CLR

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 116 Three-Bit Counters BinaryGray-code State No. of toggles State Av. Transitions/clock = 1.75 Av. Transitions/clock = 1

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 117 N-Bit Counter: Toggles in Counting Cycle Binary counter: T(binary) = 2(2 N – 1) Binary counter: T(binary) = 2(2 N – 1) Gray-code counter: T(gray) = 2 N Gray-code counter: T(gray) = 2 N T(gray)/T(binary) = 2 N-1 /(2 N – 1) → 0.5 T(gray)/T(binary) = 2 N-1 /(2 N – 1) → 0.5 BitsT(binary)T(gray)T(gray)/T(binary) ∞

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 118 FSM State Encoding Expected number of state-bit transitions: 1( ) + 2(0.1) = 1.0 Transition probability based on PI statistics State encoding can be selected using a power-based cost function. 2( ) + 1( ) = 1.6

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 119 FSM: Clock-Gating Moore machine: Outputs depend only on the state variables. Moore machine: Outputs depend only on the state variables. If a state has a self-loop in the state transition graph (STG), then clock can be stopped whenever a self-loop is to be executed. If a state has a self-loop in the state transition graph (STG), then clock can be stopped whenever a self-loop is to be executed. Sj Si Sk Xi/Zk Xk/Zk Xj/Zk Clock can be stopped when (Xk, Sk) combination occurs.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 120 Clock-Gating in Moore FSM Combinational logic Latch Clock activation logic Flip-flops PI CK PO L. Benini and G. De Micheli, Dynamic Power Management, Boston: Springer, 1998.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 121 Bus Encoding for Reduced Power Example: Four bit bus Example: Four bit bus 0000 → 1110 has three transitions → 1110 has three transitions. If bits of second pattern are inverted, then 0000 → 0001 will have only one transition. If bits of second pattern are inverted, then 0000 → 0001 will have only one transition. Bit-inversion encoding for N-bit bus: Bit-inversion encoding for N-bit bus: Number of bit transitions 0 N/2N N N/2 0 Number of bit transitions after inversion encoding

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 122 Bus-Inversion Encoding Logic Polarity decision logic Sent data Received data Bus register Polarity bit M. Stan and W. Burleson, “Bus-Invert Coding for Low Power I/O,” IEEE Trans. VLSI Systems, vol. 3, no. 1, pp , March 1995.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 123 Clock-Gating in Low-Power Flip-Flop D Q D CK

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 124 Reduced-Power Shift Register D Q D CK(f/2) multiplexer Output Flip-flops are operated at full voltage and half the clock frequency.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 125 Power Consumption of Shift Register P = C’V DD 2 f/n Degree of parallelism, n Normalized power Deg. Of parallelism Freq (MHz) Power (μW) bit shift register, 2μ CMOS C. Piguet, “Circuit and Logic Level Design,” pages in W. Nebel and J. Mermet (ed.), Low Power Design in Deep Submicron Electronics, Springer, 1997.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 126 Books on Low-Power Design (1) L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and CAD Tools, Boston: Springer, L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and CAD Tools, Boston: Springer, T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: Springer, T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: Springer, A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, New York: IEEE Press, A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, New York: IEEE Press, J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels using Formal Methods, Boston: Springer, J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels using Formal Methods, Boston: Springer, M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Boston: Springer, M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Boston: Springer, R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum Publishers, R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum Publishers, S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston: Springer, S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston: Springer, J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI Circuits, New York: Wiley- Interscience, J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI Circuits, New York: Wiley- Interscience, J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Boston: Springer, J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Boston: Springer, S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Boston: Springer, S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Boston: Springer, W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics, Boston: Springer, W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics, Boston: Springer, 1997.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 127 Books on Low-Power Design (2) N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston: Springer, M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston: Springer, C. Piguet, Low-Power Electronics Design, Boca Raton: Florida: CRC Press, C. Piguet, Low-Power Electronics Design, Boca Raton: Florida: CRC Press, J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Springer, J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Springer, S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Networks, Boston: Springer, S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Networks, Boston: Springer, K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley- Interscience, K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley- Interscience, E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE Press, E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE Press, W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits, Boston:Springer, W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits, Boston:Springer, S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Wideband CDMA System Design, Boston: Springer, S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Wideband CDMA System Design, Boston: Springer, G. Verghese and J. M. Rabaey, Low-Energy FPGAs, Boston: springer, G. Verghese and J. M. Rabaey, Low-Energy FPGAs, Boston: springer, G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:Springer, G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:Springer, K.-S. Yeo and K. Roy, Low-Voltage Low-Power Subsystems, McGraw Hill, K.-S. Yeo and K. Roy, Low-Voltage Low-Power Subsystems, McGraw Hill, 2004.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 128 Books Useful in Low-Power Design A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High- Performance Microprocessor Circuits, New York: IEEE Press, A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High- Performance Microprocessor Circuits, New York: IEEE Press, R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Third Edition, McGraw-Hill, R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Third Edition, McGraw-Hill, S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New York: McGraw-Hill, S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New York: McGraw-Hill, E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer, E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer, J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice-Hall, J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice-Hall, J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, New York: IEEE Press, J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, New York: IEEE Press, N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts: Addison-Wesley, N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts: Addison-Wesley, 2005.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 129 Problem: Bus Encoding A 1-hot encoding is to be used for reducing the capacitive power consumption of an n-bit data bus. All n bits are assumed to be independent and random. Derive a formula for the ratio of power consumptions on the encoded and the un-coded buses. Show that n ≥ 4 is essential for the 1-hot encoding to be beneficial. Reference: A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic Publishers, 1995, pp [Hint: You should be able to solve this problem without the help of the reference.]

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 130 Solution: Bus Encoding Un-coded bus: Two consecutive bits can be 00, 01, 10 and 11, each with a probability Considering only the 01 transition, which draws energy from the supply, the probability of a data pattern consuming CV 2 energy on a wire is ¼. Therefore, the average per pattern energy for all n wires of the bus is CV 2 n/4. Encoded bus: Encoded bus contains 2 n wires. The 1-hot encoding ensures that whenever there is a change in the data pattern, exactly one wire will have a 01 transition, charging its capacitance and consuming CV 2 energy. There can be 2 n possible data patterns and exactly one of these will match the previous pattern and consume no energy. Thus, the per pattern energy consumption of the bus is 0 with probability 2 –n, and CV 2 with probability 1 – 2 –n. The average per pattern energy for the 1-hot encoded bus is CV 2 (1 – 2 –n ).

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 131 Solution: Bus Encoding (Cont.) Power ratio =Encoded bus power / un-coded bus power =4(1 – 2 –n )/n → 4/n for large n For the encoding to be beneficial, the above power ratio should be less than 1. That is, 4(1 – 2 –n )/n ≤ 1, or 1 – 2 –n ≤ n/4, or n/4 ≥ 1 (approximately) → n ≥ 4. The following table shows 1-hot encoded bus power ratio as a function of bus width: n 4(1 – 2 – n )/n n = 1/ / /16