1. Copyright Agrawal, 2011Lecture 1: Introduction1 Low-Power Design of Digital VLSI Circuits Introduction to Low Power Design Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal

2. Copyright Agrawal, 2011Lecture 1: Introduction2 Course Objectives Low-power is a current need in VLSI design. Low-power is a current need in VLSI design. Learn basic ideas, concepts, theory and methods. Learn basic ideas, concepts, theory and methods. Gain experience with techniques and tools. Gain experience with techniques and tools.

3. Course Description Copyright Agrawal, 2011Lecture 1: Introduction3 This course is designed for the MTech program in VLSI at IIT, Delhi. It is patterned after a one-semester graduate-level course offered at Auburn University. A set of 16 lectures that include classroom exercises provide understanding of theoretical and practical aspects of power and energy in digital VLSI systems. The course fulfills a basic need of today’s industrial design environment. Specific topics include power components of digital CMOS circuits, power analysis, glitch elimination for reducing dynamic power, dual-threshold design for reduced static power, voltage and frequency scaling*, power management in memories* and microprocessors*, parallelism for power saving, battery management*, test power*, and ultra-low voltage (subthreshold) logic circuits*, low power technologies (domino CMOS, pass transistor logic)*, adiabatic logic*. ________________ * Not included in short course.

4. Outline Lecture 1:Introduction (37)* Number of slides Lecture 1:Introduction (37)* Number of slides Homework 1 (10 points) Homework 1 (10 points) Lecture 2:Power dissipation of CMOS Circuits (46): Lecture 2:Power dissipation of CMOS Circuits (46): Lecture 3:Power of a transition Lecture 3:Power of a transition Lecture 4:Dynamic (logic, glitch, short-circuit) power, static power Lecture 4:Dynamic (logic, glitch, short-circuit) power, static power Homework 2 (10 points) Homework 2 (10 points) Lecture 5:Gate-level power analysis (56): Lecture 5:Gate-level power analysis (56): Lecture 6:Logic simulation, delay estimation Lecture 6:Logic simulation, delay estimation Lecture 7:Transition density, Probabilistic methods Lecture 7:Transition density, Probabilistic methods Lecture 8:Power calculation Lecture 8:Power calculation Homework 3 (10 points) Homework 3 (10 points) Lecture 9:Linear Programming – A Mathematical optimization technique (44): Lecture 9:Linear Programming – A Mathematical optimization technique (44): Lecture 10:Examples of LP and ILP optimization Lecture 10:Examples of LP and ILP optimization Homework 4 (10 points) Homework 4 (10 points) Lecture 11:Gale-level power optimization (59): Lecture 11:Gale-level power optimization (59): Lecture 12:Glitch-free design for reduced dynamic power Lecture 12:Glitch-free design for reduced dynamic power Lecture 13:Dual-threshold design for reduced leakage Lecture 13:Dual-threshold design for reduced leakage Lecture 14:Examples Lecture 14:Examples Lecture 15: Multicore design for low power (23) Lecture 15: Multicore design for low power (23) Homework 5 (10 points) Homework 5 (10 points) Lecture 16:Test Power (52) Lecture 16:Test Power (52) Lecture 17:Test Power (continued) Lecture 17:Test Power (continued) EXAM (50 points) EXAM (50 points) Copyright Agrawal, 2011 Lecture 1: Introduction 4

5. Schedule July 26, 2011 – 4:00-5:30PM Lecture 1 July 26, 2011 – 4:00-5:30PM Lecture 1 July 27, 2011 – 4:00-5:30PM Lectures 2 and 3 July 27, 2011 – 4:00-5:30PM Lectures 2 and 3 July 28, 2011 – 4:00-5:30PM Lectures 4, 5 and 6 July 28, 2011 – 4:00-5:30PM Lectures 4, 5 and 6 July 29, 2011 – 4:00-5:30PM Lectures 6 (cont.), 7 and 8 July 29, 2011 – 4:00-5:30PM Lectures 6 (cont.), 7 and 8 July 30, 2011 – 4:00-5:30PM Lectures 9 and 10 July 30, 2011 – 4:00-5:30PM Lectures 9 and 10 Aug 1, 2011 – 4:00-5:30PM Lectures 11 and 12 Aug 1, 2011 – 4:00-5:30PM Lectures 11 and 12 Aug 2, 2011 – 4:00-5:30PM Lectures 13 and 14 Aug 2, 2011 – 4:00-5:30PM Lectures 13 and 14 Aug 3, 2011 – 4:00-5:30PM Lecture 15 Aug 3, 2011 – 4:00-5:30PM Lecture 15 Aug 4, 2011 – 4:00-5:30PM Lecture 16 Aug 4, 2011 – 4:00-5:30PM Lecture 16 Aug 5, 2011 – 4:00-5:30PM Lecture 17 Aug 5, 2011 – 4:00-5:30PM Lecture 17 Aug 6, 2011 – EXAM Aug 6, 2011 – EXAM Copyright Agrawal, 2011Lecture 1: Introduction5

6. Copyright Agrawal, 2011Lecture 1: Introduction6 Power Consumption of VLSI Chips Why is it a concern?

7. Copyright Agrawal, 2011Lecture 1: Introduction7 ISSCC, Feb. 2001, Keynote “Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now. “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor....” Patrick P. Gelsinger Senior Vice President General Manager Digital Enterprise Group INTEL CORP.

8. Copyright Agrawal, 2011Lecture 1: Introduction8 VLSI Chip Power Density 4004 8008 8080 8085 8086 286 386 486 Pentium® P6 1 10 100 1000 10000 19701980199020002010 Year Power Density (W/cm 2 ) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel 

9. Copyright Agrawal, 2011Lecture 1: Introduction9 SIA Roadmap for Processors (1999) Year199920022005200820112014 Feature size (nm) 180130100705035 Logic transistors/cm 2 6.2M18M39M84M180M390M Clock (GHz) 1.252.13.56.010.016.9 Chip size (mm 2 ) 340430520620750900 Power supply (V) 1.81.51.20.90.60.5 High-perf. Power (W) 90130160170175183 Source: http://www.semichips.orghttp://www.semichips.org

10. Copyright Agrawal, 2011Lecture 1: Introduction10 Recent Data Source: http://www.eetimes.com/story/OEG20040123S0041

11. Copyright Agrawal, 2011Lecture 1: Introduction11 Low-Power Design Design practices that reduce power consumption by at least one order of magnitude; in practice 50% reduction is often acceptable. Design practices that reduce power consumption by at least one order of magnitude; in practice 50% reduction is often acceptable. Low-power design methods: Low-power design methods: Algorithms and architectures Algorithms and architectures High-level and software techniques High-level and software techniques Gate and circuit-level methods Gate and circuit-level methods Test power Test power

12. Copyright Agrawal, 2011Lecture 1: Introduction12 VLSI Building Blocks Finite-state machine (FSM) Finite-state machine (FSM) Bus Bus Flip-flops and shift registers Flip-flops and shift registers Memories Memories Datapath Datapath Processors Processors Analog circuits Analog circuits RF components RF components

13. Copyright Agrawal, 2011Lecture 1: Introduction13 Specific Topics in Low-Power Power dissipation in CMOS circuits Power dissipation in CMOS circuits Device technology Device technology Low-power CMOS technologies Low-power CMOS technologies Energy recovery methods Energy recovery methods Circuit and gate level methods Circuit and gate level methods Logic synthesis Logic synthesis Dynamic power reduction techniques Dynamic power reduction techniques Leakage power reduction Leakage power reduction System level methods System level methods Microprocessors Microprocessors Arithmetic circuits Arithmetic circuits Low power memory technology Low power memory technology Test Power Test Power Power estimation Power estimation

14. Copyright Agrawal, 2011Lecture 1: Introduction14 Some Examples

15. Copyright Agrawal, 2011Lecture 1: Introduction15 State Encoding for a Counter Two-bit binary counter: Two-bit binary counter: State sequence, 00 → 01 → 10 → 11 → 00 State sequence, 00 → 01 → 10 → 11 → 00 Six bit transitions in four clock cycles Six bit transitions in four clock cycles 6/4 = 1.5 transitions per clock 6/4 = 1.5 transitions per clock Two-bit Gray-code counter Two-bit Gray-code counter State sequence, 00 → 01 → 11 → 10 → 00 State sequence, 00 → 01 → 11 → 10 → 00 Four bit transitions in four clock cycles Four bit transitions in four clock cycles 4/4 = 1.0 transition per clock 4/4 = 1.0 transition per clock Gray-code counter is more power efficient. Gray-code counter is more power efficient. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston: Kluwer Academic Publishers (now Springer), 1998.

16. Copyright Agrawal, 2011Lecture 1: Introduction16 Binary Counter: Original Encoding Present state Next state abAB 0001 0110 1011 1100 A = a’b + ab’ = a xor b B = a’b’ + ab’ = b’ ABAB a b CK CLR

17. Copyright Agrawal, 2011Lecture 1: Introduction17 Binary Counter: Gray Encoding Present state Next state abAB 0001 0111 1000 1110 A = a’b + ab = b B = a’b’ + a’b = a’ ABAB a b CK CLR

18. Copyright Agrawal, 2011Lecture 1: Introduction18 Three-Bit Counters BinaryGray-code State No. of toggles State 000-000- 00110011 01020111 01110101 10031101 10111111 11021011 11111001 00030001 Av. Transitions/clock = 1.75 Av. Transitions/clock = 1

19. Copyright Agrawal, 2011Lecture 1: Introduction19 N-Bit Counter: Toggles in Counting Cycle Binary counter: T(binary) = 2(2 N – 1) Binary counter: T(binary) = 2(2 N – 1) Gray-code counter: T(gray) = 2 N Gray-code counter: T(gray) = 2 N T(gray)/T(binary) = 2 N-1 /(2 N – 1) → 0.5 T(gray)/T(binary) = 2 N-1 /(2 N – 1) → 0.5 BitsT(binary)T(gray)T(gray)/T(binary) 1221.0 2640.6667 31480.5714 430160.5333 562320.5161 6126640.5079 ∞--0.5000

20. Copyright Agrawal, 2011Lecture 1: Introduction20 FSM State Encoding 11 0100 0.1 0.4 0.3 0.6 0.9 0.6 01 1100 0.1 0.4 0.3 0.6 0.9 0.6 Expected number of state-bit transitions: 1(0.3+0.4+0.1) + 2(0.1) = 1.0 Transition probability based on PI statistics State encoding can be selected using a power-based cost function. 2(0.3+0.4) + 1(0.1+0.1) = 1.6

21. Copyright Agrawal, 2011Lecture 1: Introduction21 FSM: Clock-Gating Moore machine: Outputs depend only on the state variables. Moore machine: Outputs depend only on the state variables. If a state has a self-loop in the state transition graph (STG), then clock can be stopped whenever a self-loop is to be executed. If a state has a self-loop in the state transition graph (STG), then clock can be stopped whenever a self-loop is to be executed. Sj Si Sk Xi/Zk Xk/Zk Xj/Zk Clock can be stopped when (Xk, Sk) combination occurs.

22. Copyright Agrawal, 2011Lecture 1: Introduction22 Clock-Gating in Moore FSM Combinational logic Latch Clock activation logic Flip-flops PI CK PO L. Benini and G. De Micheli, Dynamic Power Management, Boston: Springer, 1998.

23. Copyright Agrawal, 2011Lecture 1: Introduction23 Bus Encoding for Reduced Power Example: Four bit bus Example: Four bit bus 0000 → 1110 has three transitions. 0000 → 1110 has three transitions. If bits of second pattern are inverted, then 0000 → 0001 will have only one transition. If bits of second pattern are inverted, then 0000 → 0001 will have only one transition. Bit-inversion encoding for N-bit bus: Bit-inversion encoding for N-bit bus: Number of bit transitions 0 N/2N N N/2 0 Number of bit transitions after inversion encoding

24. Copyright Agrawal, 2011Lecture 1: Introduction24 Bus-Inversion Encoding Logic Polarity decision logic Sent data Received data Bus register Polarity bit M. Stan and W. Burleson, “Bus-Invert Coding for Low Power I/O,” IEEE Trans. VLSI Systems, vol. 3, no. 1, pp. 49-58, March 1995.

25. Copyright Agrawal, 2011Lecture 1: Introduction25 Clock-Gating in Low-Power Flip-Flop D Q D CK

26. Example: Benchmark S5378 TSMC025 CMOS technology TSMC025 CMOS technology 50ns clock 50ns clock 1,000 random vectors 1,000 random vectors Reference: J. D. Alexander, Simulation Based Power Estimation for Digital CMOS Technologies, Master’s Thesis, Auburn University, December 2008, Section 3.8. Reference: J. D. Alexander, Simulation Based Power Estimation for Digital CMOS Technologies, Master’s Thesis, Auburn University, December 2008, Section 3.8. Clock Number of comb. gates Number of flip- flops Power consumption in μW Comb. gates Flip-flopsTotal Ungated2,9581793307521,082 Gated3,31617927632308 Copyright Agrawal, 2011Lecture 1: Introduction26

27. Copyright Agrawal, 2011Lecture 1: Introduction27 Example: Shift Register D Q D CK Output

28. Copyright Agrawal, 2011Lecture 1: Introduction28 Reduced-Power Shift Register D Q D CK(f/2) multiplexer Output Flip-flops are operated at full voltage and half the clock frequency.

29. Copyright Agrawal, 2011Lecture 1: Introduction29 Power Consumption of Shift Register P = C’V DD 2 f/n Degree of parallelism, n 1 2 4 Normalized power 1.0 0.5 0.25 0.0 Deg. of parallelism Freq (MHz) Power (μW) 133.01535 216.5887 48.25738 16-bit shift register, 2μ CMOS C. Piguet, “Circuit and Logic Level Design,” pages 103-133 in W. Nebel and J. Mermet (ed.), Low Power Design in Deep Submicron Electronics, Springer, 1997.

30. Copyright Agrawal, 2011Lecture 1: Introduction30 Books on Low-Power Design (1) L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and CAD Tools, Boston: Springer, 1998. L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and CAD Tools, Boston: Springer, 1998. T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: Springer, 2002. T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: Springer, 2002. A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, 1995. A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, 1995. A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, New York: IEEE Press, 1998. A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, New York: IEEE Press, 1998. J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels using Formal Methods, Boston: Springer, 1999. J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels using Formal Methods, Boston: Springer, 1999. D. Chinnery and K. Keutzer, Closing the Power Gap Between ASIC & Custom: Tools and Techniques for Low Power Design, Springer, 2007, ISBN 0387257632, 9780387257631. D. Chinnery and K. Keutzer, Closing the Power Gap Between ASIC & Custom: Tools and Techniques for Low Power Design, Springer, 2007, ISBN 0387257632, 9780387257631. M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low- Power Digital Circuit Techniques, Boston: Springer, 1997. M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low- Power Digital Circuit Techniques, Boston: Springer, 1997.

31. Copyright Agrawal, 2011Lecture 1: Introduction31 Books on Low-Power Design (2) P. Girard, N. Nicolici and X. Wen, Power-Aware Testing and Test Strategies for Low Power Devices, Springer, 2010. P. Girard, N. Nicolici and X. Wen, Power-Aware Testing and Test Strategies for Low Power Devices, Springer, 2010. R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum Publishers, 2002. R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum Publishers, 2002. S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston: Springer, 1998. S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston: Springer, 1998. M. Keating, D. Flynn, R. Aitken, A. Gibbons and K. Shi, Low Power Methodology Manual For System-on-Chip Design, 1st ed. 2007. Corr. 2nd printing, 2007, XVI, 304 p., Hardcover, ISBN: 978-0-387- 71818-7. M. Keating, D. Flynn, R. Aitken, A. Gibbons and K. Shi, Low Power Methodology Manual For System-on-Chip Design, 1st ed. 2007. Corr. 2nd printing, 2007, XVI, 304 p., Hardcover, ISBN: 978-0-387- 71818-7. J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI Circuits, New York: Wiley-Interscience, 1999. J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI Circuits, New York: Wiley-Interscience, 1999. J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Boston: Springer, 1997. J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Boston: Springer, 1997. S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Boston: Springer, 2005. S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Boston: Springer, 2005.

32. Copyright Agrawal, 2011Lecture 1: Introduction32 Books on Low-Power Design (3) W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics, Boston: Springer, 1997. W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics, Boston: Springer, 1997. N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, 2003. N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, 2003. V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, 2005. V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, 2005. M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston: Springer, 2002. M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston: Springer, 2002. C. Piguet, Low-Power Electronics Design, Boca Raton: Florida: CRC Press, 2005. C. Piguet, Low-Power Electronics Design, Boca Raton: Florida: CRC Press, 2005. J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Springer, 1996. J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Springer, 1996. S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Networks, Boston: Springer, 2003. S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Networks, Boston: Springer, 2003.

33. Copyright Agrawal, 2011Lecture 1: Introduction33 Books on Low-Power Design (4) K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley-Interscience, 2000. K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley-Interscience, 2000. E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE Press, 1999. W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits, Boston: Springer, 1995. E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE Press, 1999. W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits, Boston: Springer, 1995. S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Wideband CDMA System Design, Boston: Springer, 1998. S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Wideband CDMA System Design, Boston: Springer, 1998. G. Verghese and J. M. Rabaey, Low-Energy FPGAs, Boston: Springer, 2001. G. Verghese and J. M. Rabaey, Low-Energy FPGAs, Boston: Springer, 2001. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston: Springer, 1998. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston: Springer, 1998. K.-S. Yeo and K. Roy, Low-Voltage Low-Power Subsystems, McGraw Hill, 2004. K.-S. Yeo and K. Roy, Low-Voltage Low-Power Subsystems, McGraw Hill, 2004.

34. Copyright Agrawal, 2011Lecture 1: Introduction34 Books Useful in Low-Power Design A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High- Performance Microprocessor Circuits, New York: IEEE Press, 2001. A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High- Performance Microprocessor Circuits, New York: IEEE Press, 2001. R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Third Edition, McGraw-Hill, 2006. R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Third Edition, McGraw-Hill, 2006. S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New York: McGraw-Hill, 1996. S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New York: McGraw-Hill, 1996. E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer, 2005. E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer, 2005. J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice- Hall, 2003. J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice- Hall, 2003. J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, New York: IEEE Press, 2004. J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, New York: IEEE Press, 2004. N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts: Addison-Wesley, 2005. N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts: Addison-Wesley, 2005.

35. Copyright Agrawal, 2011Lecture 1: Introduction35 Problem: Bus Encoding A 1-hot encoding is to be used for reducing the capacitive power consumption of an n-bit data bus. All n bits are assumed to be independent and random. Derive a formula for the ratio of power consumptions on the encoded and the un-coded buses. Show that n ≥ 4 is essential for the 1-hot encoding to be beneficial. Reference: A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic Publishers, 1995, pp. 224-225. [Hint: You should be able to solve this problem without the help of the reference.]

36. Copyright Agrawal, 2011Lecture 1: Introduction36 Solution: Bus Encoding Un-coded bus: Two consecutive bits on a wire can be 00, 01, 10 and 11, each occurring with a probability 0.25. Considering only the 0 → 1 transition, which draws energy from the supply, the probability of a data pattern consuming CV 2 energy on a wire is ¼. Therefore, the average per pattern energy for all n wires of the bus is CV 2 n/4. Encoded bus: Encoded bus contains 2 n wires. The 1-hot encoding ensures that whenever there is a change in the data pattern, exactly one wire will have a 01 transition, charging its capacitance and consuming CV 2 energy. There can be 2 n possible data patterns and exactly one of these will match the previous pattern and consume no energy. Thus, the per pattern energy consumption of the bus is 0 with probability 2 –n, and CV 2 with probability 1 – 2 –n. The average per pattern energy for the 1-hot encoded bus is CV 2 (1 – 2 –n ).

37. Copyright Agrawal, 2011Lecture 1: Introduction37 Solution: Bus Encoding (Cont.) Power ratio =Encoded bus power / un-coded bus power =4(1 – 2 –n )/n → 4/n for large n For the encoding to be beneficial, the above power ratio should be less than 1. That is, 4(1 – 2 –n )/n ≤ 1, or 1 – 2 –n ≤ n/4, or n/4 ≥ 1 (approximately) → n ≥ 4. The following table shows 1-hot encoded bus power ratio as a function of bus width: n 4(1 – 2 – n )/n n 12.000080.4981 21.5000160.2500 = 1/4 31.1670321/8 40.9375641/16