1. Damu, 2008EGE535 Spring 08, Lecture 11 EGE535 Low Power VLSI Design EGE535 Low Power VLSI Design Damu Radhakrishnan Dept of Electrical and Computer Engineering State University of New York, New Paltz, NY 12561 Tel: (845) 257-3772 damu@engr.newpaltz.edu http://www.engr.newpaltz.edu/~damu/spring2008/lowpower.htm

2. Damu, 2008EGE535 Spring 08, Lecture 12 Course Objectives Low-power is a current need in VLSI design. Low-power is a current need in VLSI design. Learn basic ideas, concepts, theory and methods. Learn basic ideas, concepts, theory and methods. Gain experience with techniques and tools. Gain experience with techniques and tools.

3. Damu, 2008EGE535 Spring 08, Lecture 13 Low-Power Design Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. Low-power design methods: Low-power design methods: Algorithms and architectures Algorithms and architectures High-level and software techniques High-level and software techniques Gate and circuit-level methods Gate and circuit-level methods Test power Test power

4. Damu, 2008EGE535 Spring 08, Lecture 14 Prerequisites Graduate Standing Graduate Standing Basic background in probability and statistics Basic background in probability and statistics Familiarity with basic MOSFET structure Familiarity with basic MOSFET structure Analyzed circuits involving transistors Analyzed circuits involving transistors Circuit simulation (PSPICE) Circuit simulation (PSPICE)

5. Damu, 2008EGE535 Spring 08, Lecture 15 Topics Covered MOSFET Basics MOSFET Basics Power dissipation in CMOS circuits Dynamic power Power dissipation in CMOS circuits Dynamic power Charging and discharging of load and parasitic capacitances Short circuit power Both nmos and pmos conducting simultaneously Static power leakage power due to reverse biased pn junctions sub-threshold conduction Low power analysis and design tools Analysis, especially power estimation in CMOS circuits (circuit, gate and architecture level) Low power analysis and design tools Analysis, especially power estimation in CMOS circuits (circuit, gate and architecture level) Simulation based approaches (highly computationally intensive) Simulation based approaches (highly computationally intensive) Probabilistic approaches (based on random processes with certain statistical characteristics) Probabilistic approaches (based on random processes with certain statistical characteristics)

6. Damu, 2008EGE535 Spring 08, Lecture 16 Topics Covered (contd.) Logic level power optimization Logic level power optimization Combinational Circuit – two level and multilevel Sequential Circuits – state assignment, logic optimizations Circuit level power optimization Circuit level power optimization Logic styles - Static, dynamic, pass transistor Latches and flip-flops Transistor sizing and ordering Drivers for large loads

7. Damu, 2008EGE535 Spring 08, Lecture 17 Topics Covered ( contd.) Low power design of sub-modules – adder, multiplier Low power design of sub-modules – adder, multiplier Case studies of arithmetic sub-modules - full adder, 4-2 compressor, adder arrays, multiplier etc. - full adder, 4-2 compressor, adder arrays, multiplier etc. Memory and Multicore design Memory hierarchy, power consumption in memory systems Memory and Multicore design Memory hierarchy, power consumption in memory systems Low power memory designs – DRAM and SRAM Low power datapath architecture Power reduction in processors System on a chip Power reduction at the chip level Bus power minimization System on a chip Power reduction at the chip level Bus power minimization Clock power Project presentations? Project presentations?

8. Damu, 2008EGE535 Spring 08, Lecture 18 Student Evaluation Homeworks (15%) Homeworks (15%) Midterms (30%) Midterms (30%) Quiz (10%) Quiz (10%) Class Project (15%) Class Project (15%) Final Exam (30%): Thursday, May 15, 2008, 2:30 – 4:30PM, REH111. Final Exam (30%): Thursday, May 15, 2008, 2:30 – 4:30PM, REH111.

9. Damu, 2008EGE535 Spring 08, Lecture 19 Power Consumption of VLSI Chips Why is it a concern?

10. Damu, 2008EGE535 Spring 08, Lecture 110 ISSCC, Feb. 2001, Keynote “Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now. “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor....” Patrick P. Gelsinger Senior Vice President General Manager Digital Enterprise Group INTEL CORP.

11. Damu, 2008EGE535 Spring 08, Lecture 111 VLSI Chip Power Density 4004 8008 8080 8085 8086 286 386 486 Pentium® P6 1 10 100 1000 10000 19701980199020002010 Year Power Density (W/cm 2 ) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel 

12. Damu, 2008EGE535 Spring 08, Lecture 112 SIA Roadmap for Processors (1999) Year199920022005200820112014 Feature size (nm) 180130100705035 Logic transistors/cm 2 6.2M18M39M84M180M390M Clock (GHz) 1.252.13.56.010.016.9 Chip size (mm 2 ) 340430520620750900 Power supply (V) 1.81.51.20.90.60.5 High-perf. Power (W) 90130160170175183 Source: http://www.semichips.orghttp://www.semichips.org

13. Damu, 2008EGE535 Spring 08, Lecture 113 Recent Data Source: http://www.eetimes.com/story/OEG20040123S0041

14. Damu, 2008EGE535 Spring 08, Lecture 114

15. Damu, 2008EGE535 Spring 08, Lecture 115 IC Design Space

16. Damu, 2008EGE535 Spring 08, Lecture 116 Why worry about power? Portability: Battery Storage Capacity is the limiting factor Multimedia Terminals Laptop Computers Digital Cellular Telephony Personal Digital Assistants Increasing Prominance of Portable Systems

17. Damu, 2008EGE535 Spring 08, Lecture 117 In July 2006, the U.S. Congress approved legislation instructing businesses to give high priority to energy efficiency as a factor in determining best value and performance for purchase of servers1. While Washington may have recently discovered that higher efficiency server not only reduces electricity bills but utilize less power for cooling, businesses have long found that these energy-efficient performance platforms provide tremendous benefits. In July 2006, the U.S. Congress approved legislation instructing businesses to give high priority to energy efficiency as a factor in determining best value and performance for purchase of servers1. While Washington may have recently discovered that higher efficiency server not only reduces electricity bills but utilize less power for cooling, businesses have long found that these energy-efficient performance platforms provide tremendous benefits.

18. Damu, 2008EGE535 Spring 08, Lecture 118 Battery progress Factor 4 over the last 10 years! 2X improvements in semiconducors in 18 months

19. Damu, 2008EGE535 Spring 08, Lecture 119 10 times more charge for lithium-ion batteries A group of researchers have formulated a way of increasing the capacity of lithium-ion batteries. The team lead by Yi Cui at Stanford University, has built a substrate out of silicon nanowiers capable of holding ten times more lithium compared to a carbon solution. Ten times more lithium means 10 times more charge. “High-performance lithium battery anodes using silicon nanowires.” Nature Nanotechnology, December 2007 New Battery Technologies New Battery Technologies Intel is investigating fuel cells and other exotic options and is particularly interested in two existing chemistries – advanced lithium polymer and zinc-alkaline, which have the potential to double battery capacities without significant increase in size or weight.

20. Damu, 2008EGE535 Spring 08, Lecture 120

21. Damu, 2008EGE535 Spring 08, Lecture 121

22. Damu, 2008EGE535 Spring 08, Lecture 122

23. Damu, 2008EGE535 Spring 08, Lecture 123 Source: S. Borkar, Intel

24. Damu, 2008EGE535 Spring 08, Lecture 124

25. Damu, 2008EGE535 Spring 08, Lecture 125

26. Damu, 2008EGE535 Spring 08, Lecture 126 Cooling Costs

27. Damu, 2008EGE535 Spring 08, Lecture 127 IEEE Spectrum, October 2007

28. Damu, 2008EGE535 Spring 08, Lecture 128

29. Damu, 2008EGE535 Spring 08, Lecture 129

30. Damu, 2008EGE535 Spring 08, Lecture 130 Books on Low-Power Design (1) L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and CAD Tools, Boston: Springer, 1998. L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and CAD Tools, Boston: Springer, 1998. T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: Springer, 2002. T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: Springer, 2002. A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, 1995. A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, 1995. A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, New York: IEEE Press, 1998. A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, New York: IEEE Press, 1998. J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels using Formal Methods, Boston: Springer, 1999. J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels using Formal Methods, Boston: Springer, 1999. M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Boston: Springer, 1997. M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Boston: Springer, 1997. R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum Publishers, 2002. R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum Publishers, 2002. S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston: Springer, 1998. S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston: Springer, 1998. J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI Circuits, New York: Wiley- Interscience, 1999. J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI Circuits, New York: Wiley- Interscience, 1999. J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Boston: Springer, 1997. J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Boston: Springer, 1997. S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Boston: Springer, 2005. S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Boston: Springer, 2005. W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics, Boston: Springer, 1997. W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics, Boston: Springer, 1997.

31. Damu, 2008EGE535 Spring 08, Lecture 131 Books on Low-Power Design (2) N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, 2003. N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, 2003. V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, 2005. V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, 2005. M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston: Springer, 2002. M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston: Springer, 2002. C. Piguet, Low-Power Electronics Design, Boca Raton: Florida: CRC Press, 2005. C. Piguet, Low-Power Electronics Design, Boca Raton: Florida: CRC Press, 2005. J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Springer, 1996. J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Springer, 1996. S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Networks, Boston: Springer, 2003. S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Networks, Boston: Springer, 2003. K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley- Interscience, 2000. K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley- Interscience, 2000. E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE Press, 1999. E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE Press, 1999. W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits, Boston:Springer, 1995. W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits, Boston:Springer, 1995. S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Wideband CDMA System Design, Boston: Springer, 1998. S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Wideband CDMA System Design, Boston: Springer, 1998. G. Verghese and J. M. Rabaey, Low-Energy FPGAs, Boston: springer, 2001. G. Verghese and J. M. Rabaey, Low-Energy FPGAs, Boston: springer, 2001. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:Springer, 1998. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:Springer, 1998. K.-S. Yeo and K. Roy, Low-Voltage Low-Power Subsystems, McGraw Hill, 2004. K.-S. Yeo and K. Roy, Low-Voltage Low-Power Subsystems, McGraw Hill, 2004.

32. Damu, 2008EGE535 Spring 08, Lecture 132 Books Useful in Low-Power Design A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High- Performance Microprocessor Circuits, New York: IEEE Press, 2001. A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High- Performance Microprocessor Circuits, New York: IEEE Press, 2001. R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Third Edition, McGraw-Hill, 2006. R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Third Edition, McGraw-Hill, 2006. S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New York: McGraw-Hill, 1996. S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New York: McGraw-Hill, 1996. E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer, 2005. E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer, 2005. J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice-Hall, 2003. J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice-Hall, 2003. J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, New York: IEEE Press, 2004. J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, New York: IEEE Press, 2004. N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts: Addison-Wesley, 2005. N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts: Addison-Wesley, 2005.