SOC Design at BWRC: A Case Study EE249 Discussion November 30, 1999 Mike Sheets

November 30, 1999SOC Design at BWRC2 Introduction BWRC research projects PicoRadio Two Chip Intercom Component based design Benefits Drawbacks Sonics and Open Core Protocol for SOC Designing with Sonics FastForward SOC Integration Tool Suite

November 30, 1999SOC Design at BWRC3 What is the BWRC? Center located in downtown Berkeley Research goals Analog RF including interface circuits and passive elements Low power digital computation Applied communications theory Design tools and methodology

November 30, 1999SOC Design at BWRC4 PicoRadio Research Project PicoRadio Network of PicoNodes Dynamic routing PicoNode Single-chip implementation of a tiny, very low power, configurable radio Sensor circuitry Cheap to manufacture

November 30, 1999SOC Design at BWRC5 PicoRadio Design Goals Examine communication vs. processing cost tradeoffs Task partitioning Resource assignment Power consumption Develop interconnect mechanisms between macro circuit blocks at the electrical level Timing of signals Specification of interface Build a single-chip implementation and perform testing Merged RF and digital

November 30, 1999SOC Design at BWRC6 Proposed PicoRadio Components Programmable architecture with dedicated DSP and analog circuitry for radio interface

November 30, 1999SOC Design at BWRC7 Two Chip Intercom (TCI) Short term sub-project of PicoRadio A little over a year long Goals Determine a design methodology for rapid and reliable chip design Explore power efficient architectures for radio design

November 30, 1999SOC Design at BWRC8 TCI Design Methodology Use VCC co-design flow (similar to POLIS) Behavior Architecture Mapping Tools VCC/POLIS – protocol stack Matlab/Simulink – baseband processing

November 30, 1999SOC Design at BWRC9 Functional Simulation Protocol stack Physical layer MAC layer Transport layer Baseband Simulated separately Theoretically could determine delays from Matlab/Simulink and annotate the VCC model

November 30, 1999SOC Design at BWRC10 Protocol Stack

November 30, 1999SOC Design at BWRC11 Benefits of VC Based Design Enables reuse of existing components Faster time to market Less error prone Test and verify each block only once Allows designer to concentrate on adding new functionality while leveraging existing design experience Components can be purchased from vendors

November 30, 1999SOC Design at BWRC12 Growing List of IP Blocks Video: MPEG, DVD, HDTV Audio: MP3, voice recognition Processors: CPUs, DSPs, Java Networking: ATM, Ethernet, ISDN, FibreChannel, SONET Bus: PCI, USB, IEEE 1394 Memory: SRAM, ROM, CAM Wireless: CDMA, TDMA Communication: modems, transceivers Coding: speech, Viterbi, Reed- Solomon Display drivers/controllers: TFT Other: sensors, encryption/decryption, GPS Power PC core: 3.1mm 2 in 0.35  ARM Core: 3.8 mm 2 in 0.35  MPEG2 Decoder: ~65k gates PCI Bus: ~8k gates Ethernet MAC: ~7k gates (soft) RSA Encryption: ~7k gates Slide from Prof. Kurt Keutzer

November 30, 1999SOC Design at BWRC13 Drawbacks of Traditional Approach No standardization of IP interface Time saved in reuse was diminished by problems with interface Clock rate Bus width Undesired interactions (side effects) Addressing scheme Correcting the interface required significant redesign

November 30, 1999SOC Design at BWRC14 Open Core Protocol (OCP) Openly licensed, core-centric protocol proposed by Sonics, Inc. Implemented as a set of signals that provide interface to core Functional superset of VSI Alliance’s Virtual Component Interface Decouples core design from architecture concerns Standardizes inter-core communication Bus independent Existing cores can be easily adapted

November 30, 1999SOC Design at BWRC15 Proposed TCI Architecture Processor (Tensilica) Memory Protocol logic (ASIC) Baseband (ASIC) Cores conform to Open Core Protocol (OCP) SiliconBackplane is synthesized by Sonics tools

November 30, 1999SOC Design at BWRC16 Hardware Mapping Cores mapped to hardware cores Communication mapped to SiliconBackplane

November 30, 1999SOC Design at BWRC17 Integration Tool Suite Components CoreCreator Facilitates encapsulation of core Protocol checker verifies compliance with OCP SOC Integrator Graphical environment to connect cores to the SiliconBackplane and configure Allows functional simulation of design SOC Builder Maps into selected technology library Generate mapped SiliconBackplane and Agents Inserts scan structures into netlist for testability

November 30, 1999SOC Design at BWRC18 Sonics FastForward Flow Source: SOCBuilder Datasheet (SOCBld ) available at

November 30, 1999SOC Design at BWRC19 Potential Drawbacks to Sonics Approach Synchronous clocking scheme Increasing chip size will mean that signals may take multiple cycles just to get from one side of the chip to the other SiliconBackplane is pipelined, so this will not change functionality However, chip-wide deskewed clocks will be a significant problem (perhaps use a locally synchronous, globally asynchronous approach) Power inefficient One large bus wastes power Could be improved using low-swing techniques

November 30, 1999SOC Design at BWRC20 Summary BWRC research demands rapid prototyping of System On Chip designs SOC can be facilitated with IP cores Open Core Protocol (OCP) standardizes core interfaces Sonics FastForward suite facilitates core creation, integration, and synthesis There are some drawbacks of Sonics design methodology