ECE 331 – Digital System Design Constraints in Logic Circuit Design (Lecture #14) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

Material to be covered … Supplemental Chapter 8: Sections 1 – 5 Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Power Consumption Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Power Consumption Each integrated circuit (IC) consumes power Power consumption can be divided into two parts: Static power consumption (PS) Dynamic power consumption (PD) Total power consumption (PT) can then be determined as PT = PS + PD Fall 2010 ECE 331 - Digital System Design

Static Power Consumption PS = VCC * ICC VCC = supply voltage ICC = supply current ICC and VCC are specified in the datasheet for the integrated circuit (IC). For TTL devices, PS is significant. For CMOS devices, PS is very small (~0 W). Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Example: 74LS08 VCC ICCH, ICCL Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Example: 74LS32 VCC ICCH, ICCL Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Example: 74HC32 VCC ICC Fall 2010 ECE 331 - Digital System Design

Example: Static Power Consumption VCC (max) ICCH (max) ICCL (max) PSH (max) PSL (max) 4.8 mA 25.2 mW 8.8 mA 46.2 mW 6.2 mA 32.55 mW 9.8 mA 51.45 mW 20 mA 120 mW 74HC32 6.00 V 74LS32 5.25 V 74LS08 Fall 2010 ECE 331 - Digital System Design

Example: Static Power Consumption The static power consumption is a function of the duty cycle. duty cycle – percentage of time in the high state PS = PS_high * thigh + PS_low * tlow where thigh = time in the high state and tlow = time in the low state Assume a 50% duty cycle PS = PS_high * 0.5 + PS_low * 0.5 Assume a 60% duty cycle PS = PS_high * 0.6 + PS_low * 0.4 Fall 2010 ECE 331 - Digital System Design

Example: Static Power Consumption PSH (max) PSL (max) 50% 60% 25.2 mW 46.2 mW 32.55 mW 51.45 mW 120 mW 74LS08 74LS32 74HC32 35.7 mW 42.0 mW 33.6 mW 40.11 mW Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Time Delay Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Time Delay A standard logic gate does not respond to a change in its input(s) instantaneously. There is, instead, a finite delay between a change in the input and a change in the output. The propagation delay of a standard logic gate is defined for two cases: tPLH = delay for output to change from low to high tPHL = delay for output to change from high to low Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Time Delay high-to-low transition low-to-high tPHL tPLH Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Time Delay The time delay (both tPLH and tPLH) for a logic gate is specified in its datasheet. The time delay is also known as the gate delay propagation delay of the logic gate. Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Example: 74LS08 tPHL, tPLH Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Example: 74LS32 tPHL, tPLH Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Example: 74HC32 tPHL, tPLH Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Time Delay The time delay of individual logic gates can be used to determine the overall propagation delay of a logic circuit. The propagation delay of a logic circuit can be used to define When the output of the logic circuit is valid. The maximum speed of the combinational logic circuit. The maximum frequency of the sequential logic circuit. Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Timing Analysis A simple timing analysis can be performed on a logic circuit assuming that only one input transitions at a time The time delay between the transition on the input and the transition on the output can be determined as follows identify the path between the input and output sum the gate delays of all gates in the path Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Timing Analysis However, Some logic circuits have more than one path between an input and the output. In some logic circuits, multiple inputs transition at the same time. The simple timing analysis will not work. Instead, perform a more conservative timing analysis using the Sum of Worst Cases (SWC) Analysis method Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Timing Analysis: SWC Identify all input-output paths (i.e. delay paths) Using the datasheet, select the worst-case gate delay for each logic gate. Select maximum of tPLH and tPHL Calculate the worst-case delay for each path Sum the gate delays of the gates in the path Select the worst case The maximum propagation delay for the circuit Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Timing Analysis: SWC Example: Using the SWC analysis method, determine the maximum propagation delay for the Exclusive-OR (XOR) Logic Circuit. Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Example: SWC A B F 74F04 74LS04 74LS08 74F08 74F32 tPLH (ns) tPHL (ns) min typ max 74LS04 9 15 10 14 74F04 2.4 3.7 6.0 1.5 3.2 5.4 74LS08 8 18 20 74F08 6.2 2.0 5.3 74F32 6.1 1.8 5.5 Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Example: SWC A B F 74F04 74LS04 74LS08 74F08 74F32 tPD = 26.1 ns tPLH (ns) tPHL (ns) min typ max 74LS04 9 15 10 14 74F04 2.4 3.7 6.0 1.5 3.2 5.4 74LS08 8 18 20 74F08 6.2 2.0 5.3 74F32 6.1 1.8 5.5 Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Example: SWC A B F 74F04 74LS04 74LS08 74F08 74F32 tPD = 27.3 ns tPLH (ns) tPHL (ns) min typ max 74LS04 9 15 10 14 74F04 2.4 3.7 6.0 1.5 3.2 5.4 74LS08 8 18 20 74F08 6.2 2.0 5.3 74F32 6.1 1.8 5.5 Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Example: SWC A B F 74F04 74LS04 74LS08 74F08 74F32 tPD = 32.1 ns tPLH (ns) tPHL (ns) min typ max 74LS04 9 15 10 14 74F04 2.4 3.7 6.0 1.5 3.2 5.4 74LS08 8 18 20 74F08 6.2 2.0 5.3 74F32 6.1 1.8 5.5 Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Example: SWC A 74LS08 B 74F04 74F32 F 74LS04 74F08 tPD = 12.3 ns tPLH (ns) tPHL (ns) min typ max 74LS04 9 15 10 14 74F04 2.4 3.7 6.0 1.5 3.2 5.4 74LS08 8 18 20 74F08 6.2 2.0 5.3 74F32 6.1 1.8 5.5 Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Example: SWC Input Output Delay (ns) A (1) F 26.1 A (2) 27.3 B (1) 32.1 B (2) 12.3 Worst Case Propagation Delay = 32.1 ns Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Transient Behavior Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Hazards When the input to a combinational logic circuit changes, unwanted switching transients may appear on the output. These transients occur when different paths from input to output have different propagation delays. Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Hazards transient Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Static 1-Hazards When analyzing combinational logic circuits for hazards we will consider the case where only one input changes at a time. Under this condition, a static 1-hazard occurs when the input change causes one product term (in a SOP expression) to transition from 1 to 0 and another product term to transition from 0 to 1. Both product terms can be transiently 0, resulting in the static 1-hazard. Fall 2010 ECE 331 - Digital System Design

Detecting Static 1-Hazards We can detect hazards in a two-level AND-OR circuit using the following procedure: Write down the sum-of-products expression for the circuit. Plot each term on the K-map and circle it. If any two adjacent 1′s are not covered by the same circle, a 1-hazard exists for the transition between the two 1′s. For an n-variable map, this transition occurs when one variable changes and the other n – 1 variables are held constant. Fall 2010 ECE 331 - Digital System Design

Detecting Static 1-Hazards B = 1 → 0 at 20ns gate delay = 10ns Static 1-Hazard Fall 2010 ECE 331 - Digital System Design

Removing Static 1-Hazards redundant, but necessary to remove hazard Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Static 0-Hazards Again, consider the case where only one input changes at a time Under this condition, a static 0-hazard occurs when the input change causes one sum term (in a POS expression) to transition from 0 to 1 and another sum term to transition from 1 to 0. Both sum terms can be transiently 1, resulting in the static 0-hazard. Fall 2010 ECE 331 - Digital System Design

Detecting Static 0-Hazards We can detect hazards in a two-level OR-AND circuit using the following procedure: Write down the product-of-sums expression for the circuit. Plot each sum term on the map and loop the zeros. If any two adjacent 0′s are not covered by the same loop, a 0-hazard exists for the transition between the two 0′s. For an n-variable map, this transition occurs when one variable changes and the other n – 1 variables are held constant. Fall 2010 ECE 331 - Digital System Design

Detecting Static 0-Hazards B = 1 D = 0 Static 0-Hazard C = 0 → 1 at 5ns AND/OR delay = 5ns NOT delay = 3ns Fall 2010 ECE 331 - Digital System Design

Removing Static 0-Hazards How many redundant gates are necessary to remove the 0-hazards? Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Hazards Exercise: Design a hazard-free combinational logic circuit to implement the following logic function F(A,B,C) = A'.C' + A.D + B.C.D' Fall 2010 ECE 331 - Digital System Design

Hazards Exercise: Design a hazard-free combinational logic circuit to implement the following logic function F(A,B,C) = (A'+C').(A+D).(B+C+D') Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Hazards Two-level AND-OR circuits (SOP) cannot have Static 0-Hazards. Why? Two-level OR-AND circuits (POS) cannot have Static 1-Hazards. Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Questions? Fall 2010 ECE 331 - Digital System Design