1. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-1 Chapter # 3: Multi-Level Combinational Logic 3.3 and 3.4 -- Time Response and Hazards / Glitches Timing Issues Chapter # 5: Arithmetic Circuits 5.2 -- Networks for Binary Addition

2. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-2 Networks for Binary Addition 1. Half Adder -- Review With twos complement numbers, addition is sufficient Half-adder Schematic

3. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-3 Networks for Binary Addition 2. Full Adder -- Review Cascaded Multi-bit Adder usually interested in adding more than two bits this motivates the need for the full adder

4. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-4 Networks for Binary Addition Full Adder S = CI  A  B CO = B CI + A CI + A B = CI (A + B) + A B

5. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-5 Networks for Binary Addition Full Adder/Half Adder A A A B B B CI S CO Alternative Implementation: 5 Gates -- cascading half adders A B + CI (A xor B) = A B + B CI + A CI Standard Approach: 6 Gates +

6. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-6 Networks for Binary Addition 3. Adder/Subtractor A - B = A + (-B) = A + B + 1 Control = 0 ==> Add Control = 1 ==> Subtract

7. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-7 For the adder circuit, Ai and Bi are summed in parallel. Bu for Si to be correct, the adder requires serial propagation of the carry outputs from the right most lowest-order stage to the left- most highest order stage. The rippling of the carry from one stage to another determines the adder’s ultimate delay. Networks for Binary Addition

8. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-8 Networks for Binary Addition 4. Carry Lookahead Circuits A A B B CI CO @0 @N @1 @N+1 @N+2 Critical delay: the propagation of carry from low to high order stages late arriving signal two gate delays to compute CO Assume the adder stages are implemented as the ‘S’ and ‘CO’ circuits on previous slide and all gates have the same delay. For the ‘S’ circuit, At time 0, Ai, Bi, and CI are presented to the adder. Within 2 gate delays, one delay for each XOR gate, S0 will be valid For ‘C0’ circuit, Ai=Bi=1, the carryout is computed in two gate delay and independent of the carry-in ==> C0 always = 1 Ai=Bi=0, the carryout is computed in two gate delay and independent of the carry-in ==> C0 always = 0 Ai  Bi, the calculation of the carry out takes three gate delays (C0 depends on the CI)

9. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-9 Networks for Binary Addition Carry Lookahead Circuits Critical delay: the propagation of carry from low to high order stages 4 stage adder final sum and carry Addition for worst case: 1111 + 0001 2 2

10. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-10 Networks for Binary Addition Carry Lookahead Circuits Critical delay: the propagation of carry from low to high order stages 1111 + 0001 worst case addition T0: Inputs to the adder are valid T2: Stage 0 carry out (C1) T4: Stage 1 carry out (C2) T6: Stage 2 carry out (C3) T8: Stage 3 carry out (C4) T0T2T4T6T8 S0, C1 ValidS1, C2 ValidS2, C3 ValidS3, C4 Valid

11. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-11 8 gate delay seems acceptable for a 4-bit adder Cascaded delays become intolerable for adders of greater widths, such as 32 or 64 bits A 32 stage adder (32 bits) take 64 gate delays to final stage carryout Led to carry look ahead schemes Ways to calculate the carry inputs in parallel rather than in series. So that it will never take more than 2 gate delays to compute any of the carry outputs. Networks for Binary Addition Carry Lookahead Circuits

12. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-12 Networks for Binary Addition Carry Lookahead Logic -- General Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here. This [asses propagates the carry across the stage Si = Ai xor Bi xor Ci = Pi xor Ci Ci+1 = Ai Bi + Ai Ci + Bi Ci = Ai Bi + Ci (Ai + Bi) = Ai Bi + Ci (Ai xor Bi) = Gi + Ci Pi Sum and Carry can be reexpressed in terms of generate/propagate: We introduce 2 new functions,

13. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-13 Networks for Binary Addition Carry Lookahead Logic Reexpress the carry logic as follows: C1 = G0 + P0 C0 C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0 C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0 Each of the carry equations can be implemented in a two-level logic network Variables are the adder inputs and carry in to stage 0 (C0)!

14. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-14 Networks for Binary Addition Carry Lookahead Implementation Adder with Propagate and Generate Outputs Pi @ 1 gate delay Ci Si @ 2 gate delays Bi Ai Gi @ 1 gate delay

15. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-15 Networks for Binary Addition Carry Lookahead Implementation Increasingly complex logic C0 P0 G0 C1 P1 G1 C2 P2 G2 C3 P3 G3 C4 When Pi and Gi are available, the subsequent C1, C2, C3, C4 are computed after two more gate delays (3 gate delays total). The sum bits can be computed in just one more gate delay.

16. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-16 Networks for Binary Addition Carry Lookahead Logic 5. Cascaded Carry Lookahead Carry lookahead logic generates individual carries sums computed much faster

17. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-17 Networks for Binary Addition Carry Lookahead Logic Cascaded Carry Lookahead 4 bit adders with internal carry lookahead second level carry lookahead unit, extends lookahead to 16 bits

18. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-18 Networks for Binary Addition 6. Carry Select Adder Redundant hardware to make carry calculation go faster compute the high order sums in parallel one addition assumes carry in = 0 the other assumes carry in = 1 C8 is selected from adder high when C4=1and Is the AND of the carries of adder low and high when C4=0.

19. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-19 3.3 Time Response in Combinational Networks emphasis on timing behavior of circuits waveforms to visualize what is happening simulation to create these waveforms momentary change of signals at the outputs: hazards can be useful— pulse shaping circuits can be a problem — glitches: incorrect circuit operation Terms: gate delay— time for change at input to cause change at output minimum delay vs. typical/nominal delay vs. maximum delay careful designers design for the worst case! rise time— time for output to transition from low to high voltage fall time— time for output to transition from high to low voltage

20. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-20 Time Response in Combinational Networks Gate Delays for Typical TTL Families Various families of TTL exhibit tradeoffs between delay and power. Faster a component, the more power it consumes. Delays depend on whether a gate is going from low to high or high to low.

21. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-21 Time Response in Combinational Networks Pulse Shaping Circuit -- It generates a periodic sequence of pulses. A' A = 0 F is not always 0! 3 gate delays (corresponding to the 3 inverters) D remains high for three gate delays after A changes from low to high A change at its input causes a short duration pulse at the output Each gate has propagation delay of 10 time units

22. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-22 Time Response in Combinational Networks Hazards/Glitches and How to Avoid Them Glitch -- unwanted pulse at the output of a combinational logic network. Hazard -- a circuit with the potential for a glitch is said to have a hazard. Occur because delay paths through the circuit experience different propagation delays Danger if logic "makes a decision" while output is unstable OR hazard output controls an asynchronous input (these respond immediately to changes rather than waiting for a synchronizing signal called a clock) Usual solutions: wait until signals are stable (by using a clock) never, never, never use circuits with asynchronous inputs design hazard-free circuits Suggest that first two approaches be used, but we'll tell you about hazard-free design since some components unavoidably have asynchronous inputs.

23. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-23 Time Response in Combinational Networks Hazards/Glitches and How to Avoid Them Kinds of Hazards Input change causes output to go from 1 to 0 to 1 when it should have remained at 1. Input change causes output to go from 0 to 1 to 0 when it should have remained at 0. Output signal has the potential to change more than once when it is expected to make a single transition from 0 to 1 OR from 1 to 0.

24. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-24 Time Response in Combinational Circuits Glitch Example F = A' D + A C' input change within product term-- G1 G1 G2 G3 A \C \A D F G1 G2 G3 A \C \A D F 1 1 1 1 1 0 0 1 1 1 1 0 0 0 ABCD = 1100 ABCD = 1101 Lets look at what happens when input changes from 1100 -> 1101

25. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-25 Time Response in Combinational Circuits Glitch Example input change that spans product terms output changes from 1 to 0 to 1 Examine K-Map: When the intial and final inputs are covered by the same prime implicant, no glitch is possible. When the input change spans prime implicants, a glitch can happen. gate delay F = A glitch happened

26. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-26 Time Response in Combinational Networks Glitch Example -- Eliminate static hazards General Strategy: add redundant prime implicant terms F = A' D + A C' becomes A' D + A C' + C' D This eliminates 1-hazard. How about 0-hazard? Re-express F in PoS form: F = (A' + C')(A + D) Glitch present! Add term: (C' + D) This expression is equivalent to the hazard-free SoP form of F

27. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-27 Time Response in Combinational Networks Glitch Example -- Eliminate static hazards Start with expression that is free of static 1-hazards F = A C' + A' D + C' D F' = (A C' + A' D + C' D)' = (A' + C) (A + D') (C + D') = A C + A C D' + C D' + A' C D' + A' D' = A C + C D' + A' D' covers all the adjacent 0's in the K-map free of static-1 and static-0 hazards! F = (A’ + C’) (C’ + D) (A + D) Work with complement: Alternative approach to eliminate 0-hazards

28. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-28 Time Response in Combinational Networks General Strategy for Static Hazard Elimination Static 1-Hazards Examine the K-map to make sure that all adjacent elements of the on-set are covered by a prime implicant. If not, add redundant prime implicants until all elements of the on- set are covered Static 0-Hazards Reexpress function in POS form Verify that adjacent elements of the off-set are covered by a common prime implicant in the PoS form. If necessary, add more prime implicants to cover any uncovered adjacencies.

29. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-29 Time Response in Combinational Networks Detecting Static Hazards in Multi-Level Circuits Map the multi-level function into a two-level form called transient output function variables and complements are treated as independent variables cannot use X + X' = 1 or X X' = 0 for simplifications F = A B C + (A + D) (A' + C') F1 = A B C + A A' + A C' + A' D + C' D Example: 2-level form ABCD: 1111 to 1110, covered by term ABC, so no 1-hazard present some static hazards are present! ABCD: 1110 to 1100, term ABC goes low while term AC' goes high 1111 to 0111 1111 to 1101 Examine K-map for static 1-hazards

30. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-30 Time Response in Combinational Networks Static 1-hazards Solution: Add redundant terms to insure all adjacent transitions are covered by terms F2 = A C' + A' D + C' D + A B + B D 1's hazards in F corrected in F2 1111 to 0111, 1111 to 1101

31. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-31 Time Response in Combinational Networks Static 0-Hazards Similar to previous case, but work with the complement of F If terms of the transient output function cover all 0 transitions, then no 0-hazards are present F = [A B C + (A + D) (A' + C')]' = (A' + B' + C') (A' D' + A C) = A' D' + A' B’ D' + A' C’ D' + A B' C = A' D' + A B' C 0-hazard on transition from 1010 to 0010 + B' C D' F3 = (A + D) (A' + B + C') (B + C' + D) 0-hazard free equivalent to F2 on last slide Add redundant term

32. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-32 Time Response in Combinational Networks Static 0-Hazards 0-Hazard Corrected in F3

33. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-33 Time Response in Combinational Networks Designing Networks for Hazard-free operation Simply place transient output function in a form that guarantees that all adjacent ones are covered by a term no term of the transient output function contains both a variable and its complement F(A,B,C,D) =  m(1,3,5,7,8,9,12,13,14,15) F = A B + A' D + B D + A C' + C' D = (A' + B + C') D + A (B + C') (factored by distributive law, which does not introduce hazards since it does not depend on the complementarity laws for its validity)

34. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-34 Time Response in Combinational Networks Dynamic Hazards -- happens because of multiple paths in the underlying multilevel network, each with its own assymetric delay Example with Dynamic Hazard Three different paths from B or B' to output ABC = 000, F = 1 to ABC = 010, F = 0different delays along the paths: G1 slow, G4 very slow Handling dynamic hazards very complex. Beyond our scope fast A multilevel network free of static hazards may still have dynamic hazards. So if a hazard-free network is needed, it is best to design a two-level static hazard-free network.

35. Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 11-35 HW #11 -- Sections 5.2, 3.3, 3.4