1. DIGITAL SYSTEMS Logic design practice Rudolf Tracht and A.J. Han Vinck

2. Logic families IC (Integrated circuit, 1960) –Many different components on one chip Logic families –Similar input, output and circuit characteristics TTL, 1960 (Transitor-Transitor logic based on bipolar junction transistor) Metal-Oxide Semiconductor field effect transitor (MOSFET, 1949) Complementary MOS: high speed, low power consumption

3. Example of TTL circuits

4. Combinational circuits Given the input: –circuit provides unique output Propagation delay –Each gate contributes a fixed delay for passing through it –Delay is different for each gate type Memoryless: no feedback

5. Transition time Transition delay: amount of time needed for a logic circuit to change its output. t r = rise time for a 0-to-1 transition t f = fall time for a 1-to-0 transition trtr tftf Ideal case approximation V hmin V Lmax

6. Slide 6 Propagation Delay Propagation delay: amount of time it takes for a change in the input signal to produce a change in the output signal Cases: maximum; minimum; typical; worst case –t PLH = delay for a 0-to-1 output change –t PHL = delay for a 1-to-0 output change Causality Input Output trtr t PHL

7. Slide 7 Delays from Data Book

8. Slide 8 Delays for Logic Families

9. Path Delay Delay along path is the sum of the delays of the gates in the path x y f

10. Critical path Path length in circuits differ Worst-case performance determined by longest path Longest path designated critical path

11. Critical path cont’d Delay and area optimum may differ! Suppose Area proportional to number of inputs –Ex:1 (AB+CD)EF –Delay: D(and2) + D(or2) + D(and3) –Number of inputs = 9 –Ex:2 ABEF + CDEF –Delay: D(and4) + D(or2) –Number of inputs = 10

12. Timing Hazards different propagation delays may lead to undesirable transient state changes, or glitches. A static-1 hazard is a set of input combinations that: –Differ only in one input variable; –Both give a logic 1 output, such that it is possible for a momentary 0 output to occur during a transition in the differing input variable. XZYXZY F A B ZABFZABF

13. Static-1 hazard cont‘d Principle: minterms change value but F stays 1 Situation 1: (...) + (...) + (...) = 1 + 0 + 0 = 1 Situation 2: (...) + (...) + (...) = 0 + 1 + 0 = 1 0011 0110 0011 0110 F = XZ‘ + YZF = XZ‘ + YZ + XY XY 00 01 11 10 01Z01Z 01Z01Z

14. Hazard cont‘d REMARKS: –Static-0 hazard may occur in a product of sums –Sum-of-products has no static-0 hazard (convince yourself) 0110 1100 1111 0011 0110 1100 1111 0011 Example:

15. Timing diagrams Timing diagram: - logical behavior of signals as a function of time - information about: delay between transitions GO ENB READY DAT GO READY DAT delay min max

16. Multi-level networks: example F = ABD+ABE+CD+CEF = AB(D+E)+C(D+E) 5 gates, 14 inputs, delay 24 gates, 9 inputs delay 3

17. Fan-in and fan-out Fan-in: # of inputs that go into a gate Fan-out: # of outputs that a gate can drive Maximum is specified - influences the design - exceeding degrades signal characteristics and functionality

18. 4-to-1 Multiplexer Y i0 i1 i2 i3 s0s1 Control inputs Data inputs Output Y = s1’s0’ i0 + s1’s0 i1 + s1s0’ i2 + s1s0 i3 s0s1Y 00i0 01i1 10i2 11i3

19. Multiplex cont‘d –Selects one of two (several) inputs based on control bit A B C Out = C‘A + CB

20. Multiplexer Multiple inputs, control input, one output Selects one of the many inputs as its output value depending upon the value of the control input. n-to-1 multiplexor has n inputs and 1 output n is typically 2, 4, 8,... Number of control inputs = log 2 n. APPLICATION: Register 1 Register 2 Register 3 Register 4 ALU control

21. Multiplex-Demultiplex-Bus Multiplex bus demultiplex selectors MUXDEMUXBUS n inputs log 2 n control inputs

22. Mux implementation of functions Example F(A,B,C) =  m(0,2,3,5) 1 A B C 0 1 2 3F 4 5 6 7 ABC F 0 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0

23. Decoders n inputs and 2 n outputs Truth table input output EN i1 i0y3 y2 y1 y0 0 x x0 0 0 0 1 0 00 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 Y i0 i1 EN Control input Output y0 y1 y2 y3

24. Example of address decoding

25. Decoders cont’d Assume F(A,B,C,D) =  m(0,5,12,15) 00 01 11 10 00 01 11 10 1010 0100 0010 0000

26. Decoder cont’d Minterm realization (useful for sparse functions) A0 B1 invertor = C··· D5 F ··· 12 ··· 15

27. Encoder Inverse functionality of a decoder Given a set of line inputs, convert it to a binary number 0i0 i1 i2 i3 i4 i5 i6 i7 y0 y1 y2 11 0 0 0 0 0 0 0 0 0 0 2y0 0 1 0 0 0 0 0 0 1 0 0 30 0 1 0 0 0 0 0 0 1 0 4y1 0 0 0 1 0 0 0 0 1 1 0 5 0 0 0 0 1 0 0 0 0 0 1 6y2 0 0 0 0 0 1 0 0 1 0 1 7 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 y0 = i1+i3+i5+i7; y1 = i2+i3+i6+i7; y2 = i4+i5+i6+i7

28. Encoder/decoder cont’d decoder to control 1 out of 2ª devices encoder used for device request of service –for multiple request: use priority encoder ex: Computer interrupt handler

29. Priority encoder i0 i1 i2 i3 i4 i5 i6 i7 A0 A1 A2 IDLE 1 0 0 0 0 0 0 0 0 0 00 x 1 0 0 0 0 0 0 1 0 00 x x 1 0 0 0 0 0 0 1 0 0 x x x 1 0 0 0 0 1 1 00 x x x x 1 0 0 0 0 0 10 x x x x x 1 0 0 1 0 10 x x x x x x 1 0 0 1 10 x x x x x x x 1 1 1 10 0 0 0 0 0 0 0 00 0 0 1 A0 = i7 + i5i6‘i7‘ + i3i4‘i5‘i6‘i7‘ + i1i2‘i3‘i4‘i5‘i6‘i7‘ Homework: write the equations for A1, A2 and IDLE Request for service Priority encoder „74x148“ idle A0 A1 A2

30. Tri state gates In bus systems, tri state logic is very useful –States are: High, Low and Disconnected H H H disable L enable L LX L enable Ξ H L disable variation H = +5 V  1 L = 0 V   High impedance := Hi-Z

31. Circuit diagram & function table EN A B C D Q2 Q1 OUT L L H H L off off Hi-Z L H H H L off off Hi-Z H L L H H on off L H H L L L off on H Enable EN C B A D Q1 Q2 OUT H L

32. Three-state buffer Acts as if it is not there (high impedance) Allows multiple sources to share a single „party line“ with a single active user –BUS Go into Hi-Z state faster than come out of –To avoid „fighting“

33. Sharing a three-state party line A B C selector 1-bit party line data “high impedance” (output disconnected) in oe out

34. Look-ahead adder Adding 10-ary numbers: 9 + 3 = 12 = 2 + 10 carry 2-ary numbers: 01 + 01 = 0 + 2 = 10; 00 + 01 = 01 carry For bit position i we have the following possibilities: x i 00010111 y i 00101011 carry c i 0 1 0 0 1 1 0 1 sum i01110001 c i+1 0 0 0 0 1 1 1 1 c i+1 = x i  y i + (x i + y i )  c i sum i = x i  y i  c i

35. Example 4 bit addition c 1 = x 0  y 0 + (x 0 + y 0 )  c 0 c 2 = x 1  y 1 + (x 1 + y 1 )  c 1 = x 1  y 1 + (x 1 + y 1 )  [x 0  y 0 + (x 0 + y 0 )  c 0 ] c 3 = x 2  y 2 + (x 2 + y 2 )  c 2 = x 2  y 2 + (x 2 + y 2 )  [ [x 1  y 1 + (x 1 + y 1 )  [x 0  y 0 + (x 0 + y 0 )  c 0 ]] c 4 = x 3  y 3 + (x 3 + y 3 )  c 3 =    To speed up, all calculations are done in parallel!

37. Look-ahead adder cont‘d (74x283) C0 X0 Y0 X1 Y1 X2 Y2 X3 Y3 S0 S1 S2 S3 C4 X4 Y4 X5 Y5 X6 Y6 X7 Y7 S4 S5 S6 S7 C8 Adding two 8-bit numbers