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**Logic Gates By Taweesak Reungpeerakul**

Chapter 2 Logic Gates By Taweesak Reungpeerakul

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**Contents Inverter AND Gate OR Gate NAND Gate NOR Gate**

XOR and XNOR Gates Integrated Circuit Logic Gates CH2

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**2.1 Inverter (INV) Symbols Truth Table In Out 0 1 1 0 Timing Diagram**

0 1 1 0 Timing Diagram Logic Expression: Out = In 1 1 CH2

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**2.2 AND Gate Symbols Truth Table Timing Diagram Logic Expression:**

A B Out Timing Diagram Logic Expression: Out = AB CH2

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**2.3 OR Gate Symbols Truth Table Timing Diagram Logic Expression:**

A B Out Timing Diagram Logic Expression: Out = A+B CH2

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**2.4 NAND Gate Symbols Truth Table Timing Diagram Logic Expression:**

A B Out Timing Diagram Logic Expression: Out = AB CH2

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**2.5 NOR Gate Symbols Truth Table Timing Diagram Logic Expression:**

A B Out Timing Diagram Logic Expression: Out = A+B CH2

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**2.6 XOR Gate Symbols Truth Table Timing Diagram Logic Expression:**

A B Out Timing Diagram Logic Expression: Out = A B+AB; AB CH2

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**XNOR Gate Symbols Truth Table Timing Diagram Logic Expression:**

A B Out Timing Diagram Logic Expression: Out = A B+AB; AB CH2

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**2.7 Integrated Circuit Logic Gates**

CMOS: Complementary Metal-Oxide Semiconductor Low Power Dissipation DC Power Supply: 5 V & 3.3 V CMOS Series: 74 + letter(s) + numbers Letters: HC, HCT = High-speed CMOS LV, LVC = Low-voltage CMOS BCT = BiCMOS (combine CMOS&TTL) Numbers: 00= Quad 2-input NAND 02= Quad 2-input NOR 04= Hex inverter TTL: Transistor-Transistor Logic Not Sensitive to Electrostatic Discharge Switching Speed DC Power Supply: 5 V TTL Series: 74 + letter(s) + numbers Letters: S = Schottky TTL LS = Low-power Schottky TTL F = Fast TTL Numbers: 08= Quad 2-input AND 10= Triple 3-input NAND 32= Quad 2-input OR CH2

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2.7 IC Logic Gate (cont.) Packages DIP IC Gate Config. CH2

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**Performance Characteristics & Parameters**

Propagation Delay Time: tP , tPHL , tPLH DC Power Supply: 3.3, 5V Power Dissipation (PD) PD = VCC (ICCH+ICCL)/2 I/O Logic Levels TTL: VIL =0.8 V, VIH =2 V VOL =0.4 V, VOH =2.4V Speed-power Product (SPP) SPP = tP*PD Fan-out and Loading Fan-out: max # gates connected at the output pin Unit loads = IOH/IIH or IOL/IIL Data Sheets CH2

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**Contents (Session 2) Boolean Operations & Expressions**

Rules of Boolean Algebra DeMorgan’s Theorems Simplification Using Boolean Algebra Standard Forms of Boolean Algebra Karnaugh Map CH2

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**2.8 Boolean Operations & Expressions**

Boolean Addition is equivalent to the OR operation. 0+0 = 0 0+1 = 1 1+0 = 1 1+1 = 1 Boolean multiplication is equivalent to the AND operation. 0·0 = 0 0·1 = 0 1·0 = 0 1·1 = 1 CH2

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**2.9 Rules of Boolean Algebra**

A+B = B+A AB = BA A+ (B+C) = (A+B)+C A(BC) = (AB)C A(B+C) = AB+AC A+0=A A·A=A A+1=1 A·A=0 A·0=0 A=A A·1=A A+A=A A+A=1 A+AB=A A+AB=A+B (A+B)(A+C)=A+BC CH2

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2.10 DeMorgan’s Theorems The complement of a product of variables is equal to the sum of the complements of the variables. XY = X + Y The complement of a sum of variables is equal to the product of complements of the variables. X + Y = X ·Y CH2

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**Examples of DeMorgan’s theorem**

Ex# 2: AB + CDE = (AB) · (CDE) = (A+B) · (CD+E) Question: A+B+C+ DE Ans: A B C+D+E Ex#1: (AB+C)(BC) = (AB+C) +(BC) = (AB)C +(B+C) = (A+B)C + B+C Question: (A+B)C D Ans: (A ·B)+C+D CH2

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**2.11 Boolean Analysis of Logic Circuits**

Truth Table A B C D (AB+C)D A AB B AB+C C D (AB+C)D CH2

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**2.12 Simplification using Boolean Algebra**

EX#1: AB+A(B+C)+B(B+C) = AB+AB+AC+BB+BC = AB + AC + B + BC = B + AC Question: AB+AC+ABC Ans: A+B C EX#2: A B C+A B C+A B C+A B C+A B C = B C+A B C+A B C+A B C = B C+ B C+A B C = BC+B(C+AC) = BC+B(C+A) = BC+B C+AB CH2

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**2.13 Standard Forms of Boolean Expressions**

Sum-of-Products (SOP): 2 or more product terms are summed by Boolean addition such as AB+ABC+AC Ex# 1: (A+B)(C+D) SOP form = AC+AD+BC+BD Ex# 2: (A + B) + C = AC + BC Standard SOP Form: all variables in the domain appear in each product term such as ABC+ABC+ABC Ex# 1: AB+ABC standard SOP = AB(C+C)+ABC = ABC+ABC+ABC Ex# 2: B+ABC = B(A+A)+ABC = AB+AB+ABC = AB(C+C)+AB(C+C)+ABC = ABC+ABC+ABC+ABC+ABC CH2

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**Standard Forms (cont.) Standard POS: Product-of-Sum (POS):**

2 or more sum terms are multiplied such as (A+B)(A+B+C) Standard POS: all variables in the domain appear in each sum term such as (A+B+C)(A+B+C) Ex# 1: (A+C)(A+B+C) standard POS = (A+C+BB)(A+B+C) =(A+B+C) (A+B+C) (A+B+C) Question: (A+C)(A+B) std. POS Ans: (A+B+C) (A+B+C) (A+B+C)(A+B+C) CH2

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**Std. SOP to std. POS Example: ABC+ABC+ABC+ABC+ABC 101 011 100 001 000**

3 variables 23 = 8 possible combinations Remained terms: 111, 110, 010 Std. POS = (A+B+C)(A+B+C)(A+B+C) CH2

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**2.14 Boolean Expressions and Truth Tables**

SOP Truth Table EX: ABC+ABC+ABC+ABC out=1 A B C Out POS Truth Table EX: (A+B+C)(A+B+C)(A+B+C) out=0 A B C Out CH2

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2.15 The Karnaugh Map The Karnaugh map is an array of cells in which each cell represents a binary value of the input variables. The number of cells is 2n, n is number of variables 3 Variables ABC ABC ABC ABC ABC ABC ABC ABC Question: 4 variables Karnaugh map CH2

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**2.16 Karnaugh Map SOP Minimization**

Ex1: Map and minimize the following std. SOP expression on a Karnaugh map: A B C+ABC+ABC+A B C AB 1 1 1 1 1 1 1 1 AC Answer: A B+AC CH2

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**SOP Minimization (cont.)**

Ex2: Map and minimize the following SOP expression on a Karnaugh map: A B +ABC+A B C B 1 1 1 1 1 1 1 1 Answer: B CH2

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**Karnaugh Map Simplification**

Grouping 1s - Each group must contain 1,2,4,8,or 16 - Each cell in a group must be adjacent to one or more cells in that same group, but all cells in the group do not have to be adjacent to each other. - Always include the largest possible number of 1s in a group - Each 1 on the map must be included in at least one group. The 1s already in a group can be included in another group as long as the overlapping groups include non-common 1s. CH2

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**Group the 1s in each of the Karnaugh maps**

ABC AC BC BC D ABC 1 1 1 1 1 1 1 1 1 A B AB C 1 1 1 1 1 1 1 1 1 1 1 1 CH2

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**2.17 Karnaugh Map POS Minimization**

Ex1: Map and minimize the following std. POS expression on a Karnaugh map: (A+B+C)(A+B+C)(A+B+C)(A+B+C) A+B A+B Answer: (A+B)(A+B) CH2

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**POS Minimization (cont.)**

Ex2: Map and minimize the following POS expression on a Karnaugh map: (A+B)(A+B+C)(A+B+C) A Answer: A CH2

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**Karnaugh maps Simplification of POS Expressions**

(B+C+D)(A+C+D)(A+B+C+D)(A+B+C+D)(A+B+C+D) (B+D) (A+C+D) (A+B) Answer: (B+D)(A+B)(A+C+D) CH2

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**Converting Between POS and SOP Using Karnaugh Map**

(B+C+D)(A+C+D)(A+B+C+D)(A+B+C+D)(A+B+C+D) (B+D) BC AD (A+C+D) 1 1 1 1 1 AB (A+B) 1 1 1 1 Min POS: (B+D)(A+B)(A+C+D) Min SOP: AB+BC+AD CH2

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**Mapping Directly from a Truth Table**

A B C Out x 1 1 x 1 Out = AB+BC CH2

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**7-segment decoding Logic**

Digit D C B A a b c d e f g x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CH2

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**Karnaugh Map Minimization of the Segment Logic**

SOP for segment a: DC BA+DCBA+DCBA+ DCBA+DCBA+DCBA+DC BA+DCBA CA 1 1 1 CA B 1 1 1 D x x x x 1 1 x x Minimum SOP expression: D+B+CA+CA CH2

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