Energy Source Lifetime Optimization for a Digital System through Power Management Department of Electrical and Computer Engineering Auburn University, Auburn, AL /10/ Manish Kulkarni & Vishwani D. Agrawal Manish Kulkarni & Vishwani Agrawal

Outline Voltage and Clock Management (DVFS) – A typical battery-powered system Battery simulation model Battery lifetime and efficiency Problem statement Proposed method – Determine operating voltage – Determine minimum battery size – Extend battery size to satisfy required lifetime Minimum energy mode operation Summary References 6/10/20152Manish Kulkarni & Vishwani Agrawal

Dynamic Voltage and Frequency Scaling (DVFS) 6/10/2015Manish Kulkarni & Vishwani Agrawal3 DC – DC Voltage Converter [9] Electronic System 4.2 V to 3.5 V Lithium- ion Battery Decoupling Capacitor VDD GND Electronic systems are not always required to be in highest performance mode Frequency and voltage can be varied Multi-voltage domains can be created which can use DVFS or power shutdown

6/10/20154 Battery Simulation Model Lithium-ion battery, unit cell capacity: N = 1 (400mAh) Battery sizes, N = 2 (800mAh), N = 3 (1.2Ah), etc. Ref: M. Chen and G. A. Rincón-Mora, “Accurate Electrical Battery Model Capable of Predicting Runtime and I-V Performance,” IEEE Transactions on Energy Conversion, vol. 21, no. 2, pp. 504–511, June Manish Kulkarni & Vishwani Agrawal

6/10/20155 Spice Simulation of Battery Model 1008 Sec Manish Kulkarni & Vishwani Agrawal For a fixed current load

Battery Efficiency Consider a 1.2 Ah battery and I Batt = 3.6A Ideal lifetime = 1.2Ah/3.6A = 1/3 hour = 1200s Actual lifetime from simulation = 1008s Efficiency= (Actual lifetime)/(Ideal lifetime) =1008/1200 =0.84 or 84% 6/10/20156Manish Kulkarni & Vishwani Agrawal

Problem Statement Selecting a battery: Battery should be capable of supplying power (current) for required system performance (clock rate). Meeting the battery lifetime requirement; lifetime is the interval between replacement or recharge. Extend battery lifetime by DVFS. Find VDD and clock rate for maximum lifetime. 6/10/20157Manish Kulkarni & Vishwani Agrawal

6/10/20158 Step 1: Determine the operating voltage based on required performance. Step 2: Determine minimum battery size for efficiency ≥ 85% Step 3: Increase battery size over the minimum size to meet lifetime requirement. Step 4: Determine a lower performance mode with maximum lifetime. Proposed Method Manish Kulkarni & Vishwani Agrawal

Determining Operating Voltage 200,000 copies of 32-bit Ripple Carry Adder (RCA) – Makes it ≈ 70 million gate circuit Consider a performance requirement of 200MHz clock, critical path delay ≤ 5ns. Circuit simulation gives, VDD = 0.6V and I Batt = 477mA. 6/10/20159Manish Kulkarni & Vishwani Agrawal

6/10/ Spice Simulation of System 200 MHz 477 mA Manish Kulkarni & Vishwani Agrawal

6/10/ Determine Minimum Battery Size For required current (477 mA) & Battery Efficiency ≥ 85 % We Choose 400 mAh Battery Manish Kulkarni & Vishwani Agrawal

Battery Lifetime vs. VDD and Clock Rate A meaningful measure of the work done by the battery is its lifetime in terms of clock cycles. For the range of voltages with correct operation, i.e., VDD = 0.1V to 1.0V, we obtain circuit delay and clock rate from HSPICE simulation. Calculate battery lifetime in clock cycles for each VDD. Find VDD and clock rate for maximum battery lifetime. 6/10/201512Manish Kulkarni & Vishwani Agrawal

6/10/ Higher Circuit Speed, Lower Battery Efficiency Simulation of 400mAh Battery Over operating voltage range of 0.1 V to 1 V (MHz) Manish Kulkarni & Vishwani Agrawal DVFS 619 Giga Cycles or 50 minutes Higher Battery Lifetime, Lower Circuit Speed

Need Longer Battery Lifetime Suppose battery lifetime for the system is to be at least 3 hours. For smallest battery, size N = 1 (400mAh) I Batt = 477mA, Efficiency ≈ 98%, Lifetime = 0.98 x 0.4/0.477 = 0.82 hour For 3 hour lifetime, battery size N = 3/0.82 = 3.65 ≈ 4. We should use a 4 cell (1600mAh) battery. 6/10/201514Manish Kulkarni & Vishwani Agrawal

6/10/ Giga Cycles or 50 minutes 2540 Giga Cycles or 205 min ( > 3 Hrs) Meeting Lifetime Requirement (MHz) Manish Kulkarni & Vishwani Agrawal

Minimum Energy Operation 6/10/ Giga Cycles or 119 hours 6630 Giga Cycles or 476 hours (MHz) Manish Kulkarni & Vishwani Agrawal

Summary Battery size VDD = 0.6V, 200MHzVDD = 0.3V*, 3.86MHz Effici. % Lifetime Effici. % Lifetime NmAh x10 3 seconds X10 9 cycles x10 3 seconds X10 9 cycles /10/ > two-times 1.Battery size should match the current need and satisfy the lifetime requirement of the system: a)Undersize battery has poor efficiency. b)Oversize battery is bulky and expensive. 2.Minimum energy mode can significantly increase battery lifetime. 3.Another case of operation with a miniature (undersized) battery is discussed in the paper. * Operation of circuits in sub-threshold voltage range (below 200 mV) have been verified [10][11] Manish Kulkarni & Vishwani Agrawal

References 1.M. Pedram and Q. Wu, “Design Considerations for Battery-Powered Electronics,” Proc. 36th Design Automation Conference, June 1999, pp. 861– L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, and R. Scarsi, “A Discrete-Time Battery Model for High-Level Power Estimation,” Proc. Conference on Design, Automation and Test in Europe, Mar. 2000, pp. 35–41. 3.M. Chen and G. A. Rincón-Mora, “Accurate Electrical Battery Model Capable of Predicting Runtime and I-V Performance,” IEEE Transactions on Energy Conversion, vol. 21, no. 2, pp. 504–511, June Simulation model: 45nm bulk CMOS, predictive technology model (PTM), 5. Simulator: Synopsys HSPICE, ds.pdf ds.pdf 7.M. Kulkarni and V. D. Agrawal, “Matching Power Source to Electronic System: A tutorial on battery simulation”, VLSI Design and Test Symposium, July M. Kulkarni, “Energy Source Lifetime Optimization for a Digital System through Power Management,” Master’s Thesis, Dec Joyce Kwong, Yogesh K. Ramadass, Naveen Verma, Anantha P. Chandrakasan, “A 65 nm Sub- Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter” IEEE Journal Of Solid- state Circuits, vol. 44, No. 1, January 2009, pp S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou, M. Singhal, M. Minuth, J. Olson, L. Nazhandali, T. Austin, D. Sylvester, and D. S. Blaauw, “Performance and variability optimization strategies in a sub-200 mV, 3.5 pJ/inst, 11 nW subthreshold processor,” in Symp. VLSI Circuits Dig., Jun. 2007, pp. 152– B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, “A variation-tolerant sub-200mV 6-T subthreshold SRAM,” IEEE Journal of Solid-State Circuits, October 2008, pp /10/201518Manish Kulkarni & Vishwani Agrawal